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AD7616BSTZ
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Analog Devices Analog To Digital Converters (ADC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+117@@ -0,0 +1,117 @@+# AD7616BSTZ++**Analog Devices** · Analog To Digital Converters (ADC) · LQFP-80(14x14)++AD7616BSTZ from Analog Devices, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND V4BGND | power_in | Analog input ground pin for V4B channel. |+| 2 | V4B | input | Channel 4 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 3 | GND V5BGND | power_in | Analog input ground pin for V5B channel. |+| 4 | V5B | input | Channel 5 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 5 | AGND | power_in | Analog power ground pin. |+| 6 | VCC | power_in | Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND. |+| 7 | V6B | input | Channel 6 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 8 | GND V6BGND | power_in | Analog input ground pin for V6B channel. |+| 9 | V7B | input | Channel 7 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 10 | GND V7BGND | power_in | Analog input ground pin for V7B channel. |+| 11 | GND V7AGND | power_in | Analog input ground pin for V7A channel. |+| 12 | V7A | input | Channel 7 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 13 | GND V6AGND | power_in | Analog input ground pin for V6A channel. |+| 14 | V6A | input | Channel 6 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 15 | VCC | power_in | Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND. |+| 16 | AGND | power_in | Analog power ground pin. |+| 17 | V5A | input | Channel 5 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 18 | GND V5AGND | power_in | Analog input ground pin for V5A channel. |+| 19 | V4A | input | Channel 4 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 20 | GND V4AGND | power_in | Analog input ground pin for V4A channel. |+| 21 | GND V3AGND | power_in | Analog input ground pin for V3A channel. |+| 22 | V3A | input | Channel 3 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 23 | GND V2AGND | power_in | Analog input ground pin for V2A channel. |+| 24 | V2A | input | Channel 2 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 25 | GND V1AGND | power_in | Analog input ground pin for V1A channel. |+| 26 | V1A | input | Channel 1 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 27 | GND V0AGND | power_in | Analog input ground pin for V0A channel. |+| 28 | V0A | input | Channel 0 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 29 | AGND | power_in | Analog power ground pin. |+| 30 | VCC | power_in | Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND. |+| 31 | REFCAP | passive | Reference voltage buffer output force/sense pin; decouple with 10 μF X5R ceramic capacitor to AGND positioned as close as possible; typical voltage 4.096 V. |+| 32 | REFGND | power_in | Reference voltage ground pin; connect to AGND. |+| 33 | REFINOUT | bidirectional | Reference voltage input/output; provides internal 2.5 V reference or accepts external 2.5 V reference; decouple with 100 nF X8R capacitor to REFINOUTGND. |+| 34 | REFINOUTGND | power_in | Reference voltage input and output ground pin. |+| 35 | REFSEL | input | Internal/external reference voltage selection logic input; high enables internal 2.5 V reference, low requires external reference on REFINOUT; state latched on complete reset. |+| 36 | RESET | input | Reset input providing complete and partial reset options selected by pulse length; hold low >1.2 μs for complete reset, 40 ns to 500 ns for partial reset. |+| 37 | SEQEN | input | Channel sequencer enable input for hardware mode; low disables sequencer, high enables sequencer; must connect to DGND in software mode. |+| 38 | HW_RNGSEL1 | input | Hardware/software mode select and hardware mode range selection input; latched on complete reset; HW_RNGSEL1/0 = 00 selects software mode, 01/10/11 selects hardware mode with ±2.5 V/±5 V/±10 V range. |+| 39 | HW_RNGSEL0 | input | Hardware/software mode select and hardware mode range selection input; latched on complete reset; HW_RNGSEL1/0 = 00 selects software mode, 01/10/11 selects hardware mode with ±2.5 V/±5 V/±10 V range. |+| 40 | SER/PAR | input | Serial/parallel interface selection logic input; low selects parallel interface, high selects serial interface; state latched on complete reset. |+| 41 | DB0 | bidirectional | Parallel output/input data bit 0; in parallel mode outputs/inputs data bit 0, must connect to DGND in serial mode. |+| 42 | DB1 | bidirectional | Parallel output/input data bit 1; in parallel mode outputs/inputs data bit 1, must connect to DGND in serial mode. |+| 43 | DB2 | bidirectional | Parallel output/input data bit 2; in parallel mode outputs/inputs data bit 2, must connect to DGND in serial mode. |+| 44 | DB3 | bidirectional | Parallel output/input data bit 3; in parallel mode outputs/inputs data bit 3, must connect to DGND in serial mode. |+| 45 | DB4/SER1W | bidirectional | Parallel data bit 4 or serial output select; in parallel mode outputs/inputs data bit 4, in serial mode controls output on SDOA only (low) or SDOA and SDOB (high); state latched on complete reset. |+| 46 | DB5/CRCEN | bidirectional | Parallel data bit 5 or CRC enable; in parallel mode outputs/inputs data bit 5, in serial mode enables CRC appended to conversion result; state latched on complete reset; must connect to DGND in software mode. |+| 47 | DB6 | bidirectional | Parallel output/input data bit 6; in parallel mode outputs/inputs data bit 6, must connect to DGND in serial mode. |+| 48 | DB7 | bidirectional | Parallel output/input data bit 7; in parallel mode outputs/inputs data bit 7, must connect to DGND in serial mode. |+| 49 | VDRIVE | power_in | Logic power input, 2.3 V to 3.6 V; determines logic interface operating voltage; decouple with 0.1 μF and 10 μF parallel capacitors. |+| 50 | DGND | power_in | Digital ground; reference point for all digital circuits, must connect to system DGND layer. |+| 51 | REGGNDD | power_in | Digital low dropout regulator ground; connect to digital LDO output decoupling capacitor. |+| 52 | REGCAPD | passive | Digital regulator voltage output decoupling pin; decouple with 10 μF capacitor to REGGNDD; typical voltage 1.89 V. |+| 53 | DB8 | bidirectional | Parallel output/input data bit 8; in parallel mode outputs/inputs data bit 8, must connect to DGND in serial mode. |+| 54 | DB9 | bidirectional | Parallel output/input data bit 9; in parallel mode outputs/inputs data bit 9, must connect to DGND in serial mode. |+| 55 | DB10/SDI | bidirectional | Parallel data bit 10 or serial data input; in parallel mode outputs/inputs data bit 10, in serial mode used as SPI data input, must connect to DGND in hardware serial mode. |+| 56 | DB11/SDOB | bidirectional | Parallel data bit 11 or serial data output B; in parallel mode outputs/inputs data bit 11, in serial mode outputs serial conversion data on SDOB when SER1W high. |+| 57 | DB12/SDOA | bidirectional | Parallel data bit 12 or serial data output A; in parallel mode outputs/inputs data bit 12, in serial mode outputs serial conversion data on SDOA. |+| 58 | DB13/OS0 | bidirectional | Parallel data bit 13 or oversampling rate select 0; in parallel mode outputs/inputs data bit 13, in hardware serial mode controls oversampling setting, must connect to DGND in software serial mode. |+| 59 | DB14/OS1 | bidirectional | Parallel data bit 14 or oversampling rate select 1; in parallel mode outputs/inputs data bit 14, in hardware serial mode controls oversampling setting, must connect to DGND in software serial mode. |+| 60 | DB15/OS2 | bidirectional | Parallel data bit 15 or oversampling rate select 2; in parallel mode outputs/inputs data bit 15, in hardware serial mode controls oversampling setting, must connect to DGND in software serial mode. |+| 61 | WR/BURST | input | Write/burst mode enable; in software parallel mode used as write control for parallel interface, in hardware mode enables burst mode for sequencer, must connect to DGND in software serial mode. |+| 62 | SCLK/RD | input | Serial clock input or parallel read control; in serial mode provides data transfer clock, in parallel mode enables output bus when CS and RD both low. |+| 63 | CS | input | Chip select, active-low logic input enabling data frame transmission; in parallel mode enables DBx output bus when CS and RD both low, in serial mode enables serial read frame. |+| 64 | CHSEL0 | input | Channel select input 0; selects next conversion input channel pair in hardware mode for channels V0A/B through V7A/B per CHSELx decoding table; must connect to DGND in software mode. |+| 65 | CHSEL1 | input | Channel select input 1; selects next conversion input channel pair in hardware mode for channels V0A/B through V7A/B per CHSELx decoding table; must connect to DGND in software mode. |+| 66 | CHSEL2 | input | Channel select input 2; selects next conversion input channel pair in hardware mode for channels V0A/B through V7A/B per CHSELx decoding table; must connect to DGND in software mode. |+| 67 | BUSY | output | Output busy; goes high when conversion starts (CONVST rising edge), stays high during conversion, falls low when conversion complete and data latched to output register. |+| 68 | CONVST | input | Conversion start input for channels A and B; initiates conversion of selected analog input when transitions from low to high; starts sequencer conversion or single conversion depending on sequencer/burst mode. |+| 69 | REGGND | power_in | Internal analog regulator ground; must connect to system AGND layer. |+| 70 | REGCAP | passive | Internal analog regulator voltage output decoupling pin; decouple with 10 μF capacitor to REGGND; typical voltage 1.87 V. |+| 71 | VCC | power_in | Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND. |+| 72 | AGND | power_in | Analog power ground pin. |+| 73 | V0B | input | Channel 0 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 74 | GND V0BGND | power_in | Analog input ground pin for V0B channel. |+| 75 | V1B | input | Channel 1 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 76 | GND V1BGND | power_in | Analog input ground pin for V1B channel. |+| 77 | V2B | input | Channel 2 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 78 | GND V2BGND | power_in | Analog input ground pin for V2B channel. |+| 79 | V3B | input | Channel 3 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input. |+| 80 | GND V3BGND | power_in | Analog input ground pin for V3B channel. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | LQFP-80(14x14) |+| Category | Data Acquisition |+| Pins | 80 |++## CAD (KiCad official)++- Symbol: `AD7616BSTZ`+- Footprint: `Package_QFP:LQFP-80_14x14mm_P0.65mm`+- 3D model: LQFP-80(14x14) (KiCad packages3D, STEP)+- 3D model files: `ad7616bstz-etched.step` / `ad7616bstz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad7616bstz.step` / `ad7616bstz.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586181464556261376) (51 pp, sha256 `21eb70526ffe725d`, retrieved 2026-09-21, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad7616bstz-datasheet.pdf)
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decouple with 0.1 μF and 10 μF capacitors to AGND."+ },+ {+ "number": "7",+ "name": "V6B",+ "type": "input",+ "description": "Channel 6 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "8",+ "name": "GND V6BGND",+ "type": "power_in",+ "description": "Analog input ground pin for V6B channel."+ },+ {+ "number": "9",+ "name": "V7B",+ "type": "input",+ "description": "Channel 7 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "10",+ "name": "GND V7BGND",+ "type": "power_in",+ "description": "Analog input ground pin for V7B channel."+ },+ {+ "number": "11",+ "name": "GND V7AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V7A channel."+ },+ {+ "number": "12",+ "name": "V7A",+ "type": "input",+ "description": "Channel 7 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "13",+ "name": "GND V6AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V6A channel."+ },+ {+ "number": "14",+ "name": "V6A",+ "type": "input",+ "description": "Channel 6 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "15",+ "name": "VCC",+ "type": "power_in",+ "description": "Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND."+ },+ {+ "number": "16",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog power ground pin."+ },+ {+ "number": "17",+ "name": "V5A",+ "type": "input",+ "description": "Channel 5 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "18",+ "name": "GND V5AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V5A channel."+ },+ {+ "number": "19",+ "name": "V4A",+ "type": "input",+ "description": "Channel 4 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "20",+ "name": "GND V4AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V4A channel."+ },+ {+ "number": "21",+ "name": "GND V3AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V3A channel."+ },+ {+ "number": "22",+ "name": "V3A",+ "type": "input",+ "description": "Channel 3 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "23",+ "name": "GND V2AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V2A channel."+ },+ {+ "number": "24",+ "name": "V2A",+ "type": "input",+ "description": "Channel 2 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "25",+ "name": "GND V1AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V1A channel."+ },+ {+ "number": "26",+ "name": "V1A",+ "type": "input",+ "description": "Channel 1 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "27",+ "name": "GND V0AGND",+ "type": "power_in",+ "description": "Analog input ground pin for V0A channel."+ },+ {+ "number": "28",+ "name": "V0A",+ "type": "input",+ "description": "Channel 0 analog input, ADC A, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "29",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog power ground pin."+ },+ {+ "number": "30",+ "name": "VCC",+ "type": "power_in",+ "description": "Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND."+ },+ {+ "number": "31",+ "name": "REFCAP",+ "type": "passive",+ "description": "Reference voltage buffer output force/sense pin; decouple with 10 μF X5R ceramic capacitor to AGND positioned as close as possible; typical voltage 4.096 V."+ },+ {+ "number": "32",+ "name": "REFGND",+ "type": "power_in",+ "description": "Reference voltage ground pin; connect to AGND."+ },+ {+ "number": "33",+ "name": "REFINOUT",+ "type": "bidirectional",+ "description": "Reference voltage input/output; provides internal 2.5 V reference or accepts external 2.5 V reference; decouple with 100 nF X8R capacitor to REFINOUTGND."+ },+ {+ "number": "34",+ "name": "REFINOUTGND",+ "type": "power_in",+ "description": "Reference voltage input and output ground pin."+ },+ {+ "number": "35",+ "name": "REFSEL",+ "type": "input",+ "description": "Internal/external reference voltage selection logic input; high enables internal 2.5 V reference, low requires external reference on REFINOUT; state latched on complete reset."+ },+ {+ "number": "36",+ "name": "RESET",+ "type": "input",+ "description": "Reset input providing complete and partial reset options selected by pulse length; hold low >1.2 μs for complete reset, 40 ns to 500 ns for partial reset."+ },+ {+ "number": "37",+ "name": "SEQEN",+ "type": "input",+ "description": "Channel sequencer enable input for hardware mode; low disables sequencer, high enables sequencer; must connect to DGND in software mode."+ },+ {+ "number": "38",+ "name": "HW_RNGSEL1",+ "type": "input",+ "description": "Hardware/software mode select and hardware mode range selection input; latched on complete reset; HW_RNGSEL1/0 = 00 selects software mode, 01/10/11 selects hardware mode with ±2.5 V/±5 V/±10 V range."+ },+ {+ "number": "39",+ "name": "HW_RNGSEL0",+ "type": "input",+ "description": "Hardware/software mode select and hardware mode range selection input; latched on complete reset; HW_RNGSEL1/0 = 00 selects software mode, 01/10/11 selects hardware mode with ±2.5 V/±5 V/±10 V range."+ },+ {+ "number": "40",+ "name": "SER/PAR",+ "type": "input",+ "description": "Serial/parallel interface selection logic input; low selects parallel interface, high selects serial interface; state latched on complete reset."+ },+ {+ "number": "41",+ "name": "DB0",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 0; in parallel mode outputs/inputs data bit 0, must connect to DGND in serial mode."+ },+ {+ "number": "42",+ "name": "DB1",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 1; in parallel mode outputs/inputs data bit 1, must connect to DGND in serial mode."+ },+ {+ "number": "43",+ "name": "DB2",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 2; in parallel mode outputs/inputs data bit 2, must connect to DGND in serial mode."+ },+ {+ "number": "44",+ "name": "DB3",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 3; in parallel mode outputs/inputs data bit 3, must connect to DGND in serial mode."+ },+ {+ "number": "45",+ "name": "DB4/SER1W",+ "type": "bidirectional",+ "description": "Parallel data bit 4 or serial output select; in parallel mode outputs/inputs data bit 4, in serial mode controls output on SDOA only (low) or SDOA and SDOB (high); state latched on complete reset."+ },+ {+ "number": "46",+ "name": "DB5/CRCEN",+ "type": "bidirectional",+ "description": "Parallel data bit 5 or CRC enable; in parallel mode outputs/inputs data bit 5, in serial mode enables CRC appended to conversion result; state latched on complete reset; must connect to DGND in software mode."+ },+ {+ "number": "47",+ "name": "DB6",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 6; in parallel mode outputs/inputs data bit 6, must connect to DGND in serial mode."+ },+ {+ "number": "48",+ "name": "DB7",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 7; in parallel mode outputs/inputs data bit 7, must connect to DGND in serial mode."+ },+ {+ "number": "49",+ "name": "VDRIVE",+ "type": "power_in",+ "description": "Logic power input, 2.3 V to 3.6 V; determines logic interface operating voltage; decouple with 0.1 μF and 10 μF parallel capacitors."+ },+ {+ "number": "50",+ "name": "DGND",+ "type": "power_in",+ "description": "Digital ground; reference point for all digital circuits, must connect to system DGND layer."+ },+ {+ "number": "51",+ "name": "REGGNDD",+ "type": "power_in",+ "description": "Digital low dropout regulator ground; connect to digital LDO output decoupling capacitor."+ },+ {+ "number": "52",+ "name": "REGCAPD",+ "type": "passive",+ "description": "Digital regulator voltage output decoupling pin; decouple with 10 μF capacitor to REGGNDD; typical voltage 1.89 V."+ },+ {+ "number": "53",+ "name": "DB8",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 8; in parallel mode outputs/inputs data bit 8, must connect to DGND in serial mode."+ },+ {+ "number": "54",+ "name": "DB9",+ "type": "bidirectional",+ "description": "Parallel output/input data bit 9; in parallel mode outputs/inputs data bit 9, must connect to DGND in serial mode."+ },+ {+ "number": "55",+ "name": "DB10/SDI",+ "type": "bidirectional",+ "description": "Parallel data bit 10 or serial data input; in parallel mode outputs/inputs data bit 10, in serial mode used as SPI data input, must connect to DGND in hardware serial mode."+ },+ {+ "number": "56",+ "name": "DB11/SDOB",+ "type": "bidirectional",+ "description": "Parallel data bit 11 or serial data output B; in parallel mode outputs/inputs data bit 11, in serial mode outputs serial conversion data on SDOB when SER1W high."+ },+ {+ "number": "57",+ "name": "DB12/SDOA",+ "type": "bidirectional",+ "description": "Parallel data bit 12 or serial data output A; in parallel mode outputs/inputs data bit 12, in serial mode outputs serial conversion data on SDOA."+ },+ {+ "number": "58",+ "name": "DB13/OS0",+ "type": "bidirectional",+ "description": "Parallel data bit 13 or oversampling rate select 0; in parallel mode outputs/inputs data bit 13, in hardware serial mode controls oversampling setting, must connect to DGND in software serial mode."+ },+ {+ "number": "59",+ "name": "DB14/OS1",+ "type": "bidirectional",+ "description": "Parallel data bit 14 or oversampling rate select 1; in parallel mode outputs/inputs data bit 14, in hardware serial mode controls oversampling setting, must connect to DGND in software serial mode."+ },+ {+ "number": "60",+ "name": "DB15/OS2",+ "type": "bidirectional",+ "description": "Parallel data bit 15 or oversampling rate select 2; in parallel mode outputs/inputs data bit 15, in hardware serial mode controls oversampling setting, must connect to DGND in software serial mode."+ },+ {+ "number": "61",+ "name": "WR/BURST",+ "type": "input",+ "description": "Write/burst mode enable; in software parallel mode used as write control for parallel interface, in hardware mode enables burst mode for sequencer, must connect to DGND in software serial mode."+ },+ {+ "number": "62",+ "name": "SCLK/RD",+ "type": "input",+ "description": "Serial clock input or parallel read control; in serial mode provides data transfer clock, in parallel mode enables output bus when CS and RD both low."+ },+ {+ "number": "63",+ "name": "CS",+ "type": "input",+ "description": "Chip select, active-low logic input enabling data frame transmission; in parallel mode enables DBx output bus when CS and RD both low, in serial mode enables serial read frame."+ },+ {+ "number": "64",+ "name": "CHSEL0",+ "type": "input",+ "description": "Channel select input 0; selects next conversion input channel pair in hardware mode for channels V0A/B through V7A/B per CHSELx decoding table; must connect to DGND in software mode."+ },+ {+ "number": "65",+ "name": "CHSEL1",+ "type": "input",+ "description": "Channel select input 1; selects next conversion input channel pair in hardware mode for channels V0A/B through V7A/B per CHSELx decoding table; must connect to DGND in software mode."+ },+ {+ "number": "66",+ "name": "CHSEL2",+ "type": "input",+ "description": "Channel select input 2; selects next conversion input channel pair in hardware mode for channels V0A/B through V7A/B per CHSELx decoding table; must connect to DGND in software mode."+ },+ {+ "number": "67",+ "name": "BUSY",+ "type": "output",+ "description": "Output busy; goes high when conversion starts (CONVST rising edge), stays high during conversion, falls low when conversion complete and data latched to output register."+ },+ {+ "number": "68",+ "name": "CONVST",+ "type": "input",+ "description": "Conversion start input for channels A and B; initiates conversion of selected analog input when transitions from low to high; starts sequencer conversion or single conversion depending on sequencer/burst mode."+ },+ {+ "number": "69",+ "name": "REGGND",+ "type": "power_in",+ "description": "Internal analog regulator ground; must connect to system AGND layer."+ },+ {+ "number": "70",+ "name": "REGCAP",+ "type": "passive",+ "description": "Internal analog regulator voltage output decoupling pin; decouple with 10 μF capacitor to REGGND; typical voltage 1.87 V."+ },+ {+ "number": "71",+ "name": "VCC",+ "type": "power_in",+ "description": "Analog power voltage, 4.75 V to 5.25 V supply for front-end amplifier and ADC core; decouple with 0.1 μF and 10 μF capacitors to AGND."+ },+ {+ "number": "72",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog power ground pin."+ },+ {+ "number": "73",+ "name": "V0B",+ "type": "input",+ "description": "Channel 0 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "74",+ "name": "GND V0BGND",+ "type": "power_in",+ "description": "Analog input ground pin for V0B channel."+ },+ {+ "number": "75",+ "name": "V1B",+ "type": "input",+ "description": "Channel 1 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "76",+ "name": "GND V1BGND",+ "type": "power_in",+ "description": "Analog input ground pin for V1B channel."+ },+ {+ "number": "77",+ "name": "V2B",+ "type": "input",+ "description": "Channel 2 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "78",+ "name": "GND V2BGND",+ "type": "power_in",+ "description": "Analog input ground pin for V2B channel."+ },+ {+ "number": "79",+ "name": "V3B",+ "type": "input",+ "description": "Channel 3 analog input, ADC B, accepts ±10 V, ±5 V, or ±2.5 V bipolar input."+ },+ {+ "number": "80",+ "name": "GND V3BGND",+ "type": "power_in",+ "description": "Analog input ground pin for V3B channel."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "2/80 pins cited to the wrong page (name found elsewhere): ['71:VCC@p15', '72:AGND@p15']"+ ],+ "pages_sent": 51,+ "cost_usd": 0.7543,+ "at": "2026-09-21T18:44:30"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586181464556261376",+ "pages": 51,+ "sha256": "21eb70526ffe725d",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 80,+ "described": 80,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}