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Initial commit: component/ad5621bksz-reel7

Ray ·bf0dd80a5e ·1mo ago
2 files changed +171
README.mdadded+42
@@ -0,0 +1,42 @@+# AD5621BKSZ-REEL7++**Analog Devices** · Digital To Analog Converters (DAC) · SOT-363-6++AD5621BKSZ-REEL7 from Analog Devices, in a SOT-363-6. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SYNC | input | Level-triggered control input (active low) for frame synchronization signal; enables input shift register when taken low, and DAC updates following 16th clock cycle unless SYNC rises before this edge to interrupt the write sequence. |+| 2 | SCLK | input | Serial clock input for clocking data into the 16-bit input shift register on falling edge; maximum data transfer rate up to 30 MHz. |+| 3 | SDIN | input | Serial data input to 16-bit shift register; data clocked into the register on the falling edge of SCLK. |+| 4 | VDD | power_in | Power supply input operating from 2.7 V to 5.5 V; should be decoupled to GND with 10 μF and 0.1 μF capacitors. |+| 5 | GND | power_in | Ground reference point for all circuitry on the AD5601/AD5611/AD5621. |+| 6 | VOUT | output | Analog output voltage from the DAC with rail-to-rail operation providing output range from 0 V to VDD. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | SOT-363-6 |+| Category | Data Acquisition |+| Pins | 6 |++## CAD (KiCad official)++- Symbol: `AD5621BKSZ-REEL7`+- Footprint: `Package_TO_SOT_SMD:SOT-363_SC-70-6`+- 3D model: SOT-363-6 (KiCad packages3D, STEP)+- 3D model files: `ad5621bksz-reel7-etched.step` / `ad5621bksz-reel7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5621bksz-reel7.step` / `ad5621bksz-reel7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202847440474112) (21 pp, sha256 `1f8185bd626f1e11`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad5621bksz-reel7-datasheet.pdf)
page.jsonadded+129
@@ -0,0 +1,129 @@+{+  "slug": "ad5621bksz-reel7",+  "version": "0.1.0",+  "type": "component",+  "description": "Analog Devices Digital To Analog Converters (DAC), SOT-363-6. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "ad5621bksz-reel7",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "ad5621bksz-reel7.kicad_sym",+    "ad5621bksz-reel7.kicad_mod",+    "ad5621bksz-reel7.glb",+    "ad5621bksz-reel7.step",+    "ad5621bksz-reel7.lbr",+    "docs/hero.png",+    "docs/ad5621bksz-reel7-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "component": {+    "mpn": "AD5621BKSZ-REEL7",+    "manufacturer": "Analog Devices",+    "package": "SOT-363-6",+    "pin_count": 6,+    "category": "Data Acquisition",+    "subcategory": "Digital To Analog Converters (DAC)",+    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202847440474112",+    "parts": {+      "symbol": "ad5621bksz-reel7.kicad_sym",+      "footprint": "ad5621bksz-reel7.kicad_mod",+      "model_3d": "ad5621bksz-reel7-etched.glb",+      "model_3d_plain": "ad5621bksz-reel7.glb",+      "model_3d_step": "ad5621bksz-reel7-etched.step",+      "model_3d_step_plain": "ad5621bksz-reel7.step",+      "lbr": "ad5621bksz-reel7.lbr"+    },+    "distributor_links": {+      "lcsc": "C73472"+    },+    "pins": [+      {+        "number": "1",+        "name": "SYNC",+        "type": "input",+        "description": "Level-triggered control input (active low) for frame synchronization signal; enables input shift register when taken low, and DAC updates following 16th clock cycle unless SYNC rises before this edge to interrupt the write sequence."+      },+      {+        "number": "2",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock input for clocking data into the 16-bit input shift register on falling edge; maximum data transfer rate up to 30 MHz."+      },+      {+        "number": "3",+        "name": "SDIN",+        "type": "input",+        "description": "Serial data input to 16-bit shift register; data clocked into the register on the falling edge of SCLK."+      },+      {+        "number": "4",+        "name": "VDD",+        "type": "power_in",+        "description": "Power supply input operating from 2.7 V to 5.5 V; should be decoupled to GND with 10 μF and 0.1 μF capacitors."+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference point for all circuitry on the AD5601/AD5611/AD5621."+      },+      {+        "number": "6",+        "name": "VOUT",+        "type": "output",+        "description": "Analog output voltage from the DAC with rail-to-rail operation providing output range from 0 V to VDD."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.2",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.2",+        "primary_model": "claude-haiku-4-5-20251001",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-4-6",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [],+        "pages_sent": 21,+        "cost_usd": 0.1939,+        "at": "2026-09-22T09:10:19"+      },+      "datasheet": {+        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586202847440474112",+        "pages": 21,+        "sha256": "1f8185bd626f1e11",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 6,+        "described": 6,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file