AD5422BREZ-REEL

@@ -0,0 +1,77 @@+# AD5422BREZ-REEL++**Analog Devices** · Digital To Analog Converters (DAC) · HTSSOP-24++AD5422BREZ-REEL from Analog Devices, in a HTSSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | AVSS | power_in | Negative analog supply. Range −3 V to −24 V. May be tied to 0 V when only a unipolar output range is used. |+| 2 | DVCC | power_in | Digital supply. Range 2.7 V to 5.5 V. Leave floating if the internal 4.5 V LDO is used (DVCC SELECT tied to GND) so this pin can be driven by the internal LDO output. |+| 3 | FAULT | output | Fault alert, active-low, open-drain output. Asserted when an open circuit is detected in current mode or when an over-temperature condition is detected. Requires an external pull-up. |+| 4 | GND | power_in | Ground reference pin (0 V). |+| 5 | CLEAR SELECT | input | Selects the voltage-output clear code loaded on a CLEAR event: zero scale or mid-scale (see Table 21). |+| 6 | CLEAR | input | Active-high asynchronous clear input. Assertion drives the current output to the low end of the selected range and the voltage output to the user-selected value (zero or mid-scale). |+| 7 | LATCH | input | Positive-edge sensitive latch. On the rising edge, the contents of the input shift register are transferred into the DAC register and the output updates. |+| 8 | SCLK | input | Serial clock input. Data is shifted into the input register on the rising edge of SCLK. Maximum clock rate 30 MHz. |+| 9 | SDIN | input | Serial data input. Data must be valid on the rising edge of SCLK. |+| 10 | SDO | output | Serial data output. Used to daisy-chain multiple devices or to read back the shift register contents. Data is clocked out on the rising edge of SCLK (see Figure 3, Figure 4). |+| 11 | GND | power_in | Ground reference pin (0 V). |+| 12 | GND | power_in | Ground reference pin (0 V). |+| 13 | RSET | passive | Optional external precision, low-drift 15 kΩ current-set resistor connection. Using an external RSET improves the IOUT temperature drift performance. |+| 14 | REFOUT | output | On-chip 5 V ± 2 mV precision reference output. |+| 15 | REFIN | input | External reference voltage input. Input range 4 V to 5 V; use REFIN = 5 V to achieve rated performance. |+| 16 | DVCC SELECT | input | When tied to GND, the internal supply is disabled and an external supply must be connected to DVCC. Leave unconnected to enable the internal 4.5 V LDO on DVCC. |+| 17 | CCOMP | passive | Optional voltage-output compensation capacitor connection. Connecting a 4 nF cap between CCOMP and VOUT allows driving up to 1 µF capacitive loads at the expense of output amplifier bandwidth and settling time. |+| 18 | NC | unconnected | No connect. Do not connect to this pin. |+| 19 | IOUT | output | Current output pin. Programmable 4-20 mA, 0-20 mA or 0-24 mA current-loop output. |+| 20 | BOOST | output | Optional external boost transistor connection. Connecting an external pass transistor reduces power dissipation in the AD5412/AD5422. |+| 21 | VOUT | output | Buffered analog voltage output. The output amplifier can drive a 1 kΩ / 2000 pF load directly. |+| 22 | +VSENSE | input | Positive load-sense (Kelvin) connection for the voltage output. |+| 23 | -VSENSE | input | Negative load-sense (Kelvin) connection for the voltage output. |+| 24 | AVDD | power_in | Positive analog supply. Range 10.8 V to 60 V. |+| 25 | EPAD | passive | Exposed thermal pad. May be tied to 0 V for unipolar output ranges, or left electrically unconnected when a supply connection is already made at AVSS. Thermally connect to a copper plane for improved heat dissipation. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | HTSSOP-24 |+| Category | Data Acquisition |+| Pins | 25 |++## Ordering variants++Same part, different packaging or reel option.++- `AD5422BREZ-REEL`+- `AD5422BREZ-REEL7`+- `AD5422BREZ-REELAREZ`+- `AD5422BREZ-REELAREZ-REEL`+- `AD5422BREZ-REELAREZ-REEL7`+- `AD5422BREZ-REELBCPZ`+- `AD5422BREZ-REELBCPZ-REEL`+- `AD5422BREZ-REELBCPZ-REEL7`+- `AD5422BREZ-REELACPZ`+- `AD5422BREZ-REELACPZ-REEL`+- `AD5422BREZ-REELACPZ-REEL7`++## CAD (KiCad official)++- Symbol: `AD5422BREZ-REEL`+- Footprint: `Package_SO:HTSSOP-24-1EP_4.4x7.8mm_P0.65mm_EP3.4x7.8mm_Mask2.4x4.68mm`+- 3D model: HTSSOP-24 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881959850688512) (44 pp, sha256 `9872399914887477`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad5422brez-reel-datasheet.pdf)

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