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AD5292BRUZ-100-RL7
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Analog Devices Digital Potentiometers, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+50@@ -0,0 +1,50 @@+# AD5292BRUZ-100-RL7++**Analog Devices** · Digital Potentiometers · TSSOP-14++AD5292BRUZ-100-RL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RESET | input | Hardware reset input activated on logic high transition; tie to VLOGIC if not used. |+| 2 | VSS | power_in | Negative power supply pin; 0 V for single-supply or −9 V to −16.5 V for dual-supply operation. |+| 3 | A | passive | Terminal A of RDAC with operating voltage range VSS ≤ VA ≤ VDD and capacitance 85 pF at 1 MHz. |+| 4 | W | passive | Wiper terminal of RDAC with operating voltage range VSS ≤ VW ≤ VDD, wiper resistance 60-100 Ω at zero code, and capacitance 65 pF at 1 MHz. |+| 5 | B | passive | Terminal B of RDAC with operating voltage range VSS ≤ VB ≤ VDD and capacitance 85 pF at 1 MHz. |+| 6 | VDD | power_in | Positive power supply pin; 9-33 V single-supply or ±9 to ±16.5 V dual-supply operating range. |+| 7 | EXT_CAP | passive | External capacitor connection requiring 1 µF capacitor with voltage rating ≥7 V for 20-TP memory operation. |+| 8 | VLOGIC | power_in | Logic supply pin with operating range 2.7-5.5 V for digital input and output buffers. |+| 9 | GND | power_in | Logic ground reference pin for digital input control signals. |+| 10 | DIN | input | Serial data input for 16-bit shift register with data clocked on falling edge of SCLK at rates up to 50 MHz. |+| 11 | SCLK | input | Serial clock input with maximum frequency 50 MHz; data clocked into shift register on falling edge. |+| 12 | SYNC | input | Frame synchronization input enabling shift register when low and updating register on rising edge after 16th clock cycle. |+| 13 | SDO | tri_state | Serial data output with open-drain topology requiring external pull-up resistor for wiper readback, memory readback, or daisy-chain operation. |+| 14 | RDY | tri_state | Active-high open-drain ready output indicating completion of RDAC register write (0.41 µs to 2.4 µs), memory program (8 ms), or readback (0.45 µs to 1.3 ms) operations. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Analog Devices |+| Package | TSSOP-14 |+| Category | Data Acquisition |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `AD5292BRUZ-100-RL7`+- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`+- 3D model: TSSOP-14 (KiCad packages3D, STEP)+- 3D model files: `ad5292bruz-100-rl7-etched.step` / `ad5292bruz-100-rl7-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ad5292bruz-100-rl7.step` / `ad5292bruz-100-rl7.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Analog Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590009032254513152) (33 pp, sha256 `9cb3d4179309fc57`, retrieved 2026-09-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/ad5292bruz-100-rl7-datasheet.pdf)
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