component
ACS724LLCTR-20AU-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
acs724llctr-20au-t: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+92−12
package.json+50−10@@ -51,25 +51,25 @@ "number": "1", "name": "IP+", "type": "passive",- "description": "Primary current path positive terminal; current flows through this terminal, internally fused, with 1.2 m\u03a9 typical resistance."+ "description": "Primary current path positive terminal; current flows through this terminal, internally fused, with 1.2 mΩ typical resistance." }, { "number": "2", "name": "IP+", "type": "passive",- "description": "Primary current path positive terminal; current flows through this terminal, internally fused, with 1.2 m\u03a9 typical resistance."+ "description": "Primary current path positive terminal; current flows through this terminal, internally fused, with 1.2 mΩ typical resistance." }, { "number": "3",- "name": "IP\u2013",+ "name": "IP–", "type": "passive",- "description": "Primary current path negative terminal; current flows through this terminal, internally fused, with 1.2 m\u03a9 typical resistance."+ "description": "Primary current path negative terminal; current flows through this terminal, internally fused, with 1.2 mΩ typical resistance." }, { "number": "4",- "name": "IP\u2013",+ "name": "IP–", "type": "passive",- "description": "Primary current path negative terminal; current flows through this terminal, internally fused, with 1.2 m\u03a9 typical resistance."+ "description": "Primary current path negative terminal; current flows through this terminal, internally fused, with 1.2 mΩ typical resistance." }, { "number": "5",@@ -81,13 +81,13 @@ "number": "6", "name": "FILTER", "type": "passive",- "description": "External capacitor connection for bandwidth filtering; forms RC circuit with internal 1.8 k\u03a9 resistance to optimize noise and resolution."+ "description": "External capacitor connection for bandwidth filtering; forms RC circuit with internal 1.8 kΩ resistance to optimize noise and resolution." }, { "number": "7", "name": "VIOUT", "type": "output",- "description": "Analog output signal proportional to primary sensed current in 0-20 A range; unidirectional output with quiescent voltage of 0.1 \u00d7 VCC nominal (approximately 0.5 V at 5 V supply)."+ "description": "Analog output signal proportional to primary sensed current in 0-20 A range; unidirectional output with quiescent voltage of 0.1 × VCC nominal (approximately 0.5 V at 5 V supply)." }, { "number": "8",@@ -128,6 +128,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "acs724llctr-20au-t.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 4.9,+ 1.75+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "acs724llctr-20au-t-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 4.9,+ 1.75+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "274a78e3365c8930ccf2dc2488147b4b05ac95719931d51180f48a6691c7b992",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -115,7 +115,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "acs724llctr-20au-t.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 4.9,+ 1.75+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "acs724llctr-20au-t-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 4.9,+ 1.75+ ],+ "zmin_mm": -0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "274a78e3365c8930ccf2dc2488147b4b05ac95719931d51180f48a6691c7b992",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -163,4 +203,4 @@ "public": true }, "updated_at": "2026-09-24T15:31:43.349Z"-}+}