component
ACS724LLCTR-20AB-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+267−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/acs724llctr-20ab-t-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+265@@ -0,0 +1,265 @@+{+ "schema": "adom.pads/1",+ "slug": "acs724llctr-20ab-t",+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm",+ "generated_from": {+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -1.905+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4"+ },+ "pad_count": 8,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "IP+",+ "type": "passive",+ "description": "Primary current sense input (positive). Tied internally to pin 2 to form the fused primary conductor (~1.2 mΩ) through which the sensed current flows. Current flowing from pins 1,2 to pins 3,4 produces a positive VIOUT slope.",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "IP+",+ "type": "passive",+ "description": "Primary current sense input (positive), internally connected to pin 1. Both pins 1 and 2 must be tied together on the PCB to carry the sensed current.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "IP-",+ "type": "passive",+ "description": "Primary current sense return (negative). Tied internally to pin 4 to form the fused primary conductor. Sensed current exits through pins 3 and 4.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "IP-",+ "type": "passive",+ "description": "Primary current sense return (negative), internally connected to pin 3. Both pins 3 and 4 must be tied together on the PCB. The IP+/IP- terminals are galvanically isolated (2400 VRMS) from the signal-side pins.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Signal ground terminal. Reference for VCC, VIOUT, and FILTER on the low-voltage side of the isolation barrier.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "FILTER",+ "type": "passive",+ "description": "External capacitor pin (CF) that, combined with the ~1.8 kΩ internal filter resistor RF(int), sets the output bandwidth (default 120 kHz small-signal BW with CF = 1 nF). Reduces noise at lower bandwidths.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "VIOUT",+ "type": "output",+ "description": "Analog output signal, ratiometric to VCC. Zero-current output ≈ VCC/2; sensitivity 100 mV/A for the ±20 A -20AB variant. Output impedance drives ≥4.7 kΩ load; saturates near VCC-0.3 V (high) / 0.3 V (low).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Device power supply terminal. 5 V single supply nominal (4.5 to 5.5 V operating range, 6 V absolute max). Typical supply current ICC = 10 mA. Bypass with 0.1 µF ceramic (CBYPASS) to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}