component
ACS724LLCTR-10AU-T
Public Made by Adomby adom
Allegro MicroSystems LLC Current Sensors, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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README.md+14@@ -45,6 +45,20 @@ ACS724LLCTR-10AU-T from Allegro MicroSystems LLC, in a SOIC-8. Pinout and pin de - Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm` - 3D model: SOIC-8 (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`acs724llctr-10au-t.step`](acs724llctr-10au-t.step) | 122 KB | You want the bare part, or you mark your own boards. |+| [`acs724llctr-10au-t-etched.step`](acs724llctr-10au-t-etched.step) | 2.7 MB | You want the part with `ACS724LLCTR-10AU-T` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 681 faces against 147 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "acs724llctr-10au-t",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "Allegro MicroSystems LLC Current Sensors, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+9−9@@ -4,7 +4,7 @@ "slug": "acs724llctr-10au-t", "title": "ACS724LLCTR-10AU-T", "brief": "Allegro MicroSystems LLC Current Sensors, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component",@@ -34,7 +34,7 @@ "number": "1", "name": "IP+", "type": "passive",- "description": "Terminal for current being sensed (positive side). Pins 1 and 2 are fused internally as one side of the primary copper conduction path (~1.2 m\u03a9). Galvanically isolated from the signal leads (pins 5-8)."+ "description": "Terminal for current being sensed (positive side). Pins 1 and 2 are fused internally as one side of the primary copper conduction path (~1.2 mΩ). Galvanically isolated from the signal leads (pins 5-8)." }, { "number": "2",@@ -64,19 +64,19 @@ "number": "6", "name": "FILTER", "type": "passive",- "description": "External bandwidth-setting capacitor terminal. A capacitor from FILTER to GND forms an RC low-pass with the internal 1.8 k\u03a9 RF(int); a 1 nF cap gives the nominal 120 kHz bandwidth. Larger CF reduces bandwidth and lowers noise."+ "description": "External bandwidth-setting capacitor terminal. A capacitor from FILTER to GND forms an RC low-pass with the internal 1.8 kΩ RF(int); a 1 nF cap gives the nominal 120 kHz bandwidth. Larger CF reduces bandwidth and lowers noise." }, { "number": "7", "name": "VIOUT", "type": "output",- "description": "Analog output signal proportional to the sensed primary current IP. Ratiometric to VCC with a quiescent output near VCC/2 and 200 mV/A sensitivity (typ) for the -10AU variant. Load: RL \u2265 4.7 k\u03a9 to GND, CL \u2264 10 nF."+ "description": "Analog output signal proportional to the sensed primary current IP. Ratiometric to VCC with a quiescent output near VCC/2 and 200 mV/A sensitivity (typ) for the -10AU variant. Load: RL ≥ 4.7 kΩ to GND, CL ≤ 10 nF." }, { "number": "8", "name": "VCC", "type": "power_in",- "description": "Device power supply terminal. 4.5 V to 5.5 V single supply, ICC typ 10 mA (max 14 mA). Bypass with 0.1 \u00b5F CBYPASS to GND close to the pin."+ "description": "Device power supply terminal. 4.5 V to 5.5 V single supply, ICC typ 10 mA (max 14 mA). Bypass with 0.1 µF CBYPASS to GND close to the pin." } ], "provenance": {@@ -150,9 +150,9 @@ "docs/hero.png", "docs/acs724llctr-10au-t-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "Allegro MicroSystems LLC Current Sensors, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D." }