ACS724KMATR-65AB-T

@@ -0,0 +1,60 @@+# ACS724KMATR-65AB-T++**Allegro MicroSystems LLC** · Current Sensors · SOIC-16-300mil++ACS724KMATR-65AB-T from Allegro MicroSystems LLC, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | IP+ | passive | Primary current sense terminal (positive side). Pins 1-4 are fused internally and form one end of the low-resistance (0.85 mΩ typ) primary conduction path. Current flowing from IP+ to IP- produces a positive output slope. |+| 2 | IP+ | passive | Primary current sense terminal (positive side). Internally fused with pins 1, 3, and 4. Must be tied together on the PCB with wide copper to carry the sensed current (60 A max continuous). |+| 3 | IP+ | passive | Primary current sense terminal (positive side). Internally fused with pins 1, 2, and 4. Tie in parallel with the other IP+ pins. |+| 4 | IP+ | passive | Primary current sense terminal (positive side). Internally fused with pins 1, 2, and 3. Tie in parallel with the other IP+ pins. |+| 5 | IP- | passive | Primary current sense terminal (negative side). Pins 5-8 are fused internally and form the return end of the primary conduction path. Tie all IP- pins together on the PCB. |+| 6 | IP- | passive | Primary current sense terminal (negative side). Internally fused with pins 5, 7, and 8. |+| 7 | IP- | passive | Primary current sense terminal (negative side). Internally fused with pins 5, 6, and 8. |+| 8 | IP- | passive | Primary current sense terminal (negative side). Internally fused with pins 5, 6, and 7. |+| 9 | NC | unconnected | No internal connection. Recommended to be left unconnected to maintain high creepage between primary and secondary sides. |+| 10 | VCC | power_in | Device power supply terminal. 4.5 to 5.5 V single supply (5 V typ), ICC = 10 mA typ (14 mA max). Decouple to GND with a 0.1 µF CBYPASS capacitor. |+| 11 | NC | unconnected | No internal connection. Recommended to connect to GND for best ESD performance. |+| 12 | VIOUT | output | Analog output signal. Ratiometric voltage proportional to the bidirectional primary current IP; sensitivity 30.75 mV/A typ at VCC = 5 V for the ±65 A range. Output slew rate 0.53 V/µs typ, response time 4 µs typ (CL = 1 nF). Drive load ≥4.7 kΩ; output capacitance ≤10 nF. |+| 13 | FILTER | passive | External filter capacitor terminal that sets output bandwidth. Internal filter resistor RF(INT) = 1.7 kΩ forms an RC low-pass with an external CF (e.g. 1 nF for ~120 kHz internal BW). Larger CF reduces bandwidth and noise. |+| 14 | NC | unconnected | No internal connection. Recommended to connect to GND for best ESD performance. |+| 15 | GND | power_in | Signal ground terminal. Return for VCC bypass and VIOUT load. |+| 16 | NC | unconnected | No internal connection. Recommended to be left unconnected to maintain high creepage between primary and secondary sides. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Allegro MicroSystems LLC |+| Package | SOIC-16-300mil |+| Category | Sensor |+| Pins | 16 |++## Ordering variants++- `ACS724KMATR-65AB-TACS724KMATR-12AB-T`+- `ACS724KMATR-65AB-TACS724KMATR-20AB-T`+- `ACS724KMATR-65AB-TACS724KMATR-30AB-T`+- `ACS724KMATR-65AB-TACS724KMATR-30AU-T`+- `ACS724KMATR-65AB-TACS724KMATR-50AB-T`+- `ACS724KMATR-65AB-T`++## CAD (KiCad official)++- Symbol: `ACS724KMATR-65AB-T`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Allegro MicroSystems LLC datasheet](docs/acs724kmatr-65ab-t-datasheet.pdf) (20 pp, sha256 `e71e378342f2422c`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/acs724kmatr-65ab-t-datasheet.pdf)

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