← Commit history

acs724kmatr-65ab-t: factory component page (tier=lcsc)

Ray ·2e3004eb05 ·1mo ago ·parent 1c7201f
1 file changed +164−8
page.json+164−8
@@ -1,13 +1,174 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "acs724kmatr-65ab-t",+  "title": "ACS724KMATR-65AB-T",+  "brief": "Allegro MicroSystems LLC Current Sensors, SOIC-16-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Allegro MicroSystems LLC Current Sensors, SOIC-16-300mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "sensor",     "acs724kmatr-65ab-t"   ],+  "component": {+    "mpn": "ACS724KMATR-65AB-T",+    "manufacturer": "Allegro MicroSystems LLC",+    "package": "SOIC-16-300mil",+    "pin_count": 16,+    "category": "Sensor",+    "subcategory": "Current Sensors",+    "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9d5a725db119fdc7aebd6141314aac9e.pdf",+    "parts": {+      "symbol": "acs724kmatr-65ab-t.kicad_sym",+      "footprint": "acs724kmatr-65ab-t.kicad_mod",+      "model_3d": "acs724kmatr-65ab-t.glb",+      "model_3d_step": "acs724kmatr-65ab-t.step",+      "lbr": "acs724kmatr-65ab-t.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "IP+",+        "type": "passive",+        "description": "Primary current sense terminal (positive side). Pins 1-4 are fused internally and form one end of the low-resistance (0.85 m\u03a9 typ) primary conduction path. Current flowing from IP+ to IP- produces a positive output slope."+      },+      {+        "number": "2",+        "name": "IP+",+        "type": "passive",+        "description": "Primary current sense terminal (positive side). Internally fused with pins 1, 3, and 4. Must be tied together on the PCB with wide copper to carry the sensed current (60 A max continuous)."+      },+      {+        "number": "3",+        "name": "IP+",+        "type": "passive",+        "description": "Primary current sense terminal (positive side). Internally fused with pins 1, 2, and 4. Tie in parallel with the other IP+ pins."+      },+      {+        "number": "4",+        "name": "IP+",+        "type": "passive",+        "description": "Primary current sense terminal (positive side). Internally fused with pins 1, 2, and 3. Tie in parallel with the other IP+ pins."+      },+      {+        "number": "5",+        "name": "IP-",+        "type": "passive",+        "description": "Primary current sense terminal (negative side). Pins 5-8 are fused internally and form the return end of the primary conduction path. Tie all IP- pins together on the PCB."+      },+      {+        "number": "6",+        "name": "IP-",+        "type": "passive",+        "description": "Primary current sense terminal (negative side). Internally fused with pins 5, 7, and 8."+      },+      {+        "number": "7",+        "name": "IP-",+        "type": "passive",+        "description": "Primary current sense terminal (negative side). Internally fused with pins 5, 6, and 8."+      },+      {+        "number": "8",+        "name": "IP-",+        "type": "passive",+        "description": "Primary current sense terminal (negative side). Internally fused with pins 5, 6, and 7."+      },+      {+        "number": "9",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection. Recommended to be left unconnected to maintain high creepage between primary and secondary sides."+      },+      {+        "number": "10",+        "name": "VCC",+        "type": "power_in",+        "description": "Device power supply terminal. 4.5 to 5.5 V single supply (5 V typ), ICC = 10 mA typ (14 mA max). Decouple to GND with a 0.1 \u00b5F CBYPASS capacitor."+      },+      {+        "number": "11",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection. Recommended to connect to GND for best ESD performance."+      },+      {+        "number": "12",+        "name": "VIOUT",+        "type": "output",+        "description": "Analog output signal. Ratiometric voltage proportional to the bidirectional primary current IP; sensitivity 30.75 mV/A typ at VCC = 5 V for the \u00b165 A range. Output slew rate 0.53 V/\u00b5s typ, response time 4 \u00b5s typ (CL = 1 nF). Drive load \u22654.7 k\u03a9; output capacitance \u226410 nF."+      },+      {+        "number": "13",+        "name": "FILTER",+        "type": "passive",+        "description": "External filter capacitor terminal that sets output bandwidth. Internal filter resistor RF(INT) = 1.7 k\u03a9 forms an RC low-pass with an external CF (e.g. 1 nF for ~120 kHz internal BW). Larger CF reduces bandwidth and noise."+      },+      {+        "number": "14",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection. Recommended to connect to GND for best ESD performance."+      },+      {+        "number": "15",+        "name": "GND",+        "type": "power_in",+        "description": "Signal ground terminal. Return for VCC bypass and VIOUT load."+      },+      {+        "number": "16",+        "name": "NC",+        "type": "unconnected",+        "description": "No internal connection. Recommended to be left unconnected to maintain high creepage between primary and secondary sides."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://datasheet.lcsc.com/datasheet/pdf/9d5a725db119fdc7aebd6141314aac9e.pdf",+        "pages": 20,+        "sha256": "e71e378342f2422c",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 16,+        "described": 16,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Allegro MicroSystems LLC",+      "Package": "SOIC-16-300mil",+      "Category": "Sensor",+      "Pins": "16"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "acs724kmatr-65ab-t"+  ],+  "discovery_pitch": "ACS724KMATR-65AB-T (Allegro MicroSystems LLC) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +186,5 @@     "docs/acs724kmatr-65ab-t-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file