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A3941KLPTR-T
Public Made by Adomby adom
Allegro MicroSystems LLC Global Sourcing Parts, TSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+65@@ -0,0 +1,65 @@+# A3941KLPTR-T++**Allegro MicroSystems LLC** · Global Sourcing Parts · TSSOP-28-EP++A3941KLPTR-T from Allegro MicroSystems LLC, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VDRAIN | input | Low-current sense input (≤250 µA) from high-side FET drain for measuring bridge voltage at the positive supply connection point. |+| 2 | LSS | power_in | Low-side return path for FET gate discharge current, connected independently with low impedance to common source of low-side FETs. |+| 3 | GLB | output | Low-side gate drive output for phase B MOSFET with 60-150 ns propagation delay and 3-4 Ω pulldown on-resistance. |+| 4 | SB | passive | Load connection B (motor phase terminal) sensing bridge voltage and providing negative supply reference for phase B bootstrap circuit. |+| 5 | GHB | output | High-side gate drive output for phase B MOSFET powered from phase B bootstrap capacitor CB, with source-to-pin voltage VCB - 0.2 V minimum. |+| 6 | CB | passive | Phase B bootstrap capacitor connection, charged to approximately 13 V (VREG) when SB is low, with working voltage limit 16 V. |+| 7 | VREG | power_in | Regulated 13 V output (12.5-13.75 V at VBB > 9 V) supplying power to low-side gate drivers and bootstrap charging circuits. |+| 8 | VREG | power_in | Regulated 13 V output (duplicate connection), second supply pin for power distribution. |+| 9 | CA | passive | Phase A bootstrap capacitor connection, charged to approximately 13 V (VREG) when SA is low, with working voltage limit 16 V. |+| 10 | GHA | output | High-side gate drive output for phase A MOSFET powered from phase A bootstrap capacitor CA, with source-to-pin voltage VCA - 0.2 V minimum. |+| 11 | SA | passive | Load connection A (motor phase terminal) sensing bridge voltage and providing negative supply reference for phase A bootstrap circuit. |+| 12 | GLA | output | Low-side gate drive output for phase A MOSFET with 60-150 ns propagation delay and 3-4 Ω pulldown on-resistance. |+| 13 | VBB | power_in | Main power supply input, 5.5-50 V operating range (7-50 V functional), requires reverse voltage protection and 100 nF decoupling capacitor. |+| 14 | VBB | power_in | Main power supply input (duplicate connection), second supply pin for current distribution. |+| 15 | CP2 | passive | Charge pump capacitor negative terminal, requires minimum 220 nF external capacitor between CP1 and CP2 when VBB < 16 V. |+| 16 | CP1 | passive | Charge pump capacitor positive terminal, requires minimum 220 nF external capacitor between CP1 and CP2 when VBB < 16 V. |+| 17 | GND | power_in | Ground reference for digital logic and analog circuits, requires independent low-impedance connection to motor supply common. |+| 18 | GND | power_in | Ground reference (duplicate connection), second ground pin for low-impedance returns. |+| 19 | PHASE | input | Phase control input (0-5.5 V logic, 300-500 mV hysteresis) selecting load current direction or PWM input for four-quadrant control. |+| 20 | V5 | power_in | 5 V logic supply output (4.5-5.5 V) from integrated regulator, requires minimum 100 nF decoupling capacitor between V5 and GND. |+| 21 | SR | input | Synchronous rectification enable input (0-5.5 V logic, 300-500 mV hysteresis) turning on complementary MOSFETs during PWM off-time. |+| 22 | PWML | input | Low-side PWM control input (0-5.5 V logic, 300-500 mV hysteresis) for slow or fast decay operation. |+| 23 | PWMH | input | High-side PWM control input (0-5.5 V logic, 300-500 mV hysteresis) for slow or fast decay operation. |+| 24 | RESET | input | Active-low reset input (0-5.5 V logic, 200 mV hysteresis, 50 kΩ internal pulldown) enabling sleep mode and clearing latched faults. |+| 25 | FF1 | tri_state | Open-drain fault flag output (<0.4 V when fault present, <1 µA leakage current) indicating overtemperature or combined fault conditions. |+| 26 | FF2 | tri_state | Open-drain fault flag output (<0.4 V when fault present, <1 µA leakage current) indicating short-circuit, undervoltage, or combined faults. |+| 27 | RDEAD | input | Dead-time setting input (resistor 3 kΩ to 240 kΩ or V5 connection) controlling cross-conduction prevention delay from 180 ns to 6 µs. |+| 28 | VDSTH | input | VDS threshold comparison input (0.1-2 V range) for FET short-circuit detection, disabled when voltage exceeds 4.95 V disable threshold. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Allegro MicroSystems LLC |+| Package | TSSOP-28-EP |+| Category | Global Sourcing Parts |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `A3941KLPTR-T`+- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`+- 3D model: TSSOP-28-EP (KiCad packages3D, STEP)+- 3D model files: `a3941klptr-t-etched.step` / `a3941klptr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `a3941klptr-t.step` / `a3941klptr-t.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Allegro MicroSystems LLC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881832846757888) (21 pp, sha256 `0134af8d609fc7c3`, retrieved 2026-09-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/a3941klptr-t-datasheet.pdf)
page.jsonadded+271@@ -0,0 +1,271 @@+{+ "slug": "a3941klptr-t",+ "version": "0.1.0",+ "type": "component",+ "description": "Allegro MicroSystems LLC Global Sourcing Parts, TSSOP-28-EP. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "global sourcing parts",+ "a3941klptr-t",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "a3941klptr-t.kicad_sym",+ "a3941klptr-t.kicad_mod",+ "a3941klptr-t.glb",+ "a3941klptr-t.step",+ "a3941klptr-t.lbr",+ "docs/hero.png",+ "docs/a3941klptr-t-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "A3941KLPTR-T",+ "manufacturer": "Allegro MicroSystems LLC",+ "package": "TSSOP-28-EP",+ "pin_count": 29,+ "category": "Global Sourcing Parts",+ "subcategory": "Global Sourcing Parts",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881832846757888",+ "parts": {+ "symbol": "a3941klptr-t.kicad_sym",+ "footprint": "a3941klptr-t.kicad_mod",+ "model_3d": "a3941klptr-t-etched.glb",+ "model_3d_plain": "a3941klptr-t.glb",+ "model_3d_step": "a3941klptr-t-etched.step",+ "model_3d_step_plain": "a3941klptr-t.step",+ "lbr": "a3941klptr-t.lbr"+ },+ "distributor_links": {+ "lcsc": "C83516"+ },+ "pins": [+ {+ "number": "1",+ "name": "VDRAIN",+ "type": "input",+ "description": "Low-current sense input (≤250 µA) from high-side FET drain for measuring bridge voltage at the positive supply connection point."+ },+ {+ "number": "2",+ "name": "LSS",+ "type": "power_in",+ "description": "Low-side return path for FET gate discharge current, connected independently with low impedance to common source of low-side FETs."+ },+ {+ "number": "3",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate drive output for phase B MOSFET with 60-150 ns propagation delay and 3-4 Ω pulldown on-resistance."+ },+ {+ "number": "4",+ "name": "SB",+ "type": "passive",+ "description": "Load connection B (motor phase terminal) sensing bridge voltage and providing negative supply reference for phase B bootstrap circuit."+ },+ {+ "number": "5",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate drive output for phase B MOSFET powered from phase B bootstrap capacitor CB, with source-to-pin voltage VCB - 0.2 V minimum."+ },+ {+ "number": "6",+ "name": "CB",+ "type": "passive",+ "description": "Phase B bootstrap capacitor connection, charged to approximately 13 V (VREG) when SB is low, with working voltage limit 16 V."+ },+ {+ "number": "7",+ "name": "VREG",+ "type": "power_in",+ "description": "Regulated 13 V output (12.5-13.75 V at VBB > 9 V) supplying power to low-side gate drivers and bootstrap charging circuits."+ },+ {+ "number": "8",+ "name": "VREG",+ "type": "power_in",+ "description": "Regulated 13 V output (duplicate connection), second supply pin for power distribution."+ },+ {+ "number": "9",+ "name": "CA",+ "type": "passive",+ "description": "Phase A bootstrap capacitor connection, charged to approximately 13 V (VREG) when SA is low, with working voltage limit 16 V."+ },+ {+ "number": "10",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate drive output for phase A MOSFET powered from phase A bootstrap capacitor CA, with source-to-pin voltage VCA - 0.2 V minimum."+ },+ {+ "number": "11",+ "name": "SA",+ "type": "passive",+ "description": "Load connection A (motor phase terminal) sensing bridge voltage and providing negative supply reference for phase A bootstrap circuit."+ },+ {+ "number": "12",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate drive output for phase A MOSFET with 60-150 ns propagation delay and 3-4 Ω pulldown on-resistance."+ },+ {+ "number": "13",+ "name": "VBB",+ "type": "power_in",+ "description": "Main power supply input, 5.5-50 V operating range (7-50 V functional), requires reverse voltage protection and 100 nF decoupling capacitor."+ },+ {+ "number": "14",+ "name": "VBB",+ "type": "power_in",+ "description": "Main power supply input (duplicate connection), second supply pin for current distribution."+ },+ {+ "number": "15",+ "name": "CP2",+ "type": "passive",+ "description": "Charge pump capacitor negative terminal, requires minimum 220 nF external capacitor between CP1 and CP2 when VBB < 16 V."+ },+ {+ "number": "16",+ "name": "CP1",+ "type": "passive",+ "description": "Charge pump capacitor positive terminal, requires minimum 220 nF external capacitor between CP1 and CP2 when VBB < 16 V."+ },+ {+ "number": "17",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for digital logic and analog circuits, requires independent low-impedance connection to motor supply common."+ },+ {+ "number": "18",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (duplicate connection), second ground pin for low-impedance returns."+ },+ {+ "number": "19",+ "name": "PHASE",+ "type": "input",+ "description": "Phase control input (0-5.5 V logic, 300-500 mV hysteresis) selecting load current direction or PWM input for four-quadrant control."+ },+ {+ "number": "20",+ "name": "V5",+ "type": "power_in",+ "description": "5 V logic supply output (4.5-5.5 V) from integrated regulator, requires minimum 100 nF decoupling capacitor between V5 and GND."+ },+ {+ "number": "21",+ "name": "SR",+ "type": "input",+ "description": "Synchronous rectification enable input (0-5.5 V logic, 300-500 mV hysteresis) turning on complementary MOSFETs during PWM off-time."+ },+ {+ "number": "22",+ "name": "PWML",+ "type": "input",+ "description": "Low-side PWM control input (0-5.5 V logic, 300-500 mV hysteresis) for slow or fast decay operation."+ },+ {+ "number": "23",+ "name": "PWMH",+ "type": "input",+ "description": "High-side PWM control input (0-5.5 V logic, 300-500 mV hysteresis) for slow or fast decay operation."+ },+ {+ "number": "24",+ "name": "RESET",+ "type": "input",+ "description": "Active-low reset input (0-5.5 V logic, 200 mV hysteresis, 50 kΩ internal pulldown) enabling sleep mode and clearing latched faults."+ },+ {+ "number": "25",+ "name": "FF1",+ "type": "tri_state",+ "description": "Open-drain fault flag output (<0.4 V when fault present, <1 µA leakage current) indicating overtemperature or combined fault conditions."+ },+ {+ "number": "26",+ "name": "FF2",+ "type": "tri_state",+ "description": "Open-drain fault flag output (<0.4 V when fault present, <1 µA leakage current) indicating short-circuit, undervoltage, or combined faults."+ },+ {+ "number": "27",+ "name": "RDEAD",+ "type": "input",+ "description": "Dead-time setting input (resistor 3 kΩ to 240 kΩ or V5 connection) controlling cross-conduction prevention delay from 180 ns to 6 µs."+ },+ {+ "number": "28",+ "name": "VDSTH",+ "type": "input",+ "description": "VDS threshold comparison input (0.1-2 V range) for FET short-circuit detection, disabled when voltage exceeds 4.95 V disable threshold."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 29 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint",+ "13/29 pins cited to the wrong page (name found elsewhere): ['4:SB@p8', '11:SA@p8', '12:GLA@p8', '14:VBB@p7']"+ ],+ "pages_sent": 21,+ "cost_usd": 0.4069,+ "at": "2026-09-22T05:11:54"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588881832846757888",+ "pages": 21,+ "sha256": "0134af8d609fc7c3",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}