8002A

@@ -62,6 +62,18 @@   <smd name="6" x="2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -70,7 +82,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="8002A">@@ -108,7 +120,13 @@         <connect gate="G$1" pin="VDD" pad="6"/>         <connect gate="G$1" pin="VO1" pad="5"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="8002A" constant="no"/>+          <attribute name="MANUFACTURER" value="IDCHIP" constant="no"/>+          <attribute name="LCSC_PN" value="C329448" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>

@@ -26,43 +26,45 @@       "model_3d_step": "8002a.step",       "lbr": "8002a.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C329448"+    },     "pins": [       {         "number": "1",         "name": "SD",         "type": "input",-        "description": "Shutdown control input. Logic HIGH (VIH = 1.5V to VDD) disables the amplifier and puts the chip into low-power mode (~10μA typical, 16μA max); logic LOW (VIL = 0 to 1V) enables normal operation. Pin is high-impedance internally with no pull-up/pull-down - must not be left floating (tie to GND if unused)."+        "description": "Shutdown control input. Logic HIGH (VIH = 1.5V to VDD) disables the amplifier and puts the chip into low-power mode (~10\u03bcA typical, 16\u03bcA max); logic LOW (VIL = 0 to 1V) enables normal operation. Pin is high-impedance internally with no pull-up/pull-down - must not be left floating (tie to GND if unused)."       },       {         "number": "2",         "name": "BYP",         "type": "passive",-        "description": "Bypass pin - internal VDD/2 mid-supply reference output. Connect a bypass capacitor (typ. 1μF) from this pin to GND to filter the mid-rail reference and improve PSRR and low-frequency THD+N."+        "description": "Bypass pin - internal VDD/2 mid-supply reference output. Connect a bypass capacitor (typ. 1\u03bcF) from this pin to GND to filter the mid-rail reference and improve PSRR and low-frequency THD+N."       },       {         "number": "3",         "name": "NC",         "type": "unconnected",-        "description": "No connection. Datasheet features list explicitly states '芯片第3脚无功能' (Pin 3 has no function). Leave unconnected on the PCB."+        "description": "No connection. Datasheet features list explicitly states '\u82af\u7247\u7b2c3\u811a\u65e0\u529f\u80fd' (Pin 3 has no function). Leave unconnected on the PCB."       },       {         "number": "4",         "name": "INN",         "type": "input",-        "description": "Inverting analog audio input to the input op-amp stage. Closed-loop gain of the first stage is set by external Rf (feedback) and Ri (input) resistors; overall differential BTL gain AVD = 2*(Rf/Ri). AC-couple the source through Ci (typ. 0.39μF) which forms a high-pass filter with Ri (fC = 1/(2πRiCi))."+        "description": "Inverting analog audio input to the input op-amp stage. Closed-loop gain of the first stage is set by external Rf (feedback) and Ri (input) resistors; overall differential BTL gain AVD = 2*(Rf/Ri). AC-couple the source through Ci (typ. 0.39\u03bcF) which forms a high-pass filter with Ri (fC = 1/(2\u03c0RiCi))."       },       {         "number": "5",         "name": "VO1",         "type": "output",-        "description": "Analog audio output 1 (one side of the bridge-tied-load speaker output). Biased at VDD/2 mid-rail; drives one terminal of the 4Ω or 8Ω speaker directly with no output coupling capacitor required. Signal is 180° out of phase with VO2."+        "description": "Analog audio output 1 (one side of the bridge-tied-load speaker output). Biased at VDD/2 mid-rail; drives one terminal of the 4\u03a9 or 8\u03a9 speaker directly with no output coupling capacitor required. Signal is 180\u00b0 out of phase with VO2."       },       {         "number": "6",         "name": "VDD",         "type": "power_in",-        "description": "Positive supply input. Recommended operating range 2.0V to 5.5V (absolute max 6V). Quiescent supply current IDD ≈ 15mA (no load, VDD=5V). Decouple with 10μF and 0.1μF capacitors placed close to the pin."+        "description": "Positive supply input. Recommended operating range 2.0V to 5.5V (absolute max 6V). Quiescent supply current IDD \u2248 15mA (no load, VDD=5V). Decouple with 10\u03bcF and 0.1\u03bcF capacitors placed close to the pin."       },       {         "number": "7",@@ -74,7 +76,7 @@         "number": "8",         "name": "VO2",         "type": "output",-        "description": "Analog audio output 2 (other side of the bridge-tied-load speaker output). Biased at VDD/2 mid-rail; the internal second-stage op-amp is fixed at unity inverting gain via two internal 20kΩ resistors, so VO2 is 180° out of phase with VO1. Connect the speaker directly between VO1 and VO2."+        "description": "Analog audio output 2 (other side of the bridge-tied-load speaker output). Biased at VDD/2 mid-rail; the internal second-stage op-amp is fixed at unity inverting gain via two internal 20k\u03a9 resistors, so VO2 is 180\u00b0 out of phase with VO1. Connect the speaker directly between VO1 and VO2."       }     ],     "provenance": {