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Show the shared chip-thumbnailer cache widget and reusable artwork manifest

John Lauer ·85b7e937bf ·28d ago ·parent 9d7ebc2
2 files changed +19−3
README.md+11−2
@@ -24,13 +24,22 @@ Canonical adom-lbr and KiCad files are in Files. Model pose/pin-1 seating, deriv  ## 3D reference artwork -The derived display retains the source model geometry and materials, with a recorded rigid pose into Adom Z-up footprint coordinates. Nonphysical reference layers show teal dashed copper-pad boundaries at 50% opacity, silkscreen at 30% opacity, and signal names at 50% opacity. Labels follow the canonical pin-to-pad mapping. Unnamed nonpolarized passive connections are labeled “Terminal”; no polarity or signal function is invented. Original manufacturer STEP files remain unchanged.+The derived display retains the source model geometry and materials, with a recorded rigid pose into Adom Z-up footprint coordinates. Nonphysical reference layers show teal dashed copper-pad boundaries at 50% opacity, silkscreen at 30% opacity, and signal names at 50% opacity. Labels follow the canonical pin-to-pad mapping. Unnamed nonpolarized passive connections are labeled “Terminal”; no polarity or signal function is invented. Original manufacturer STEP files remain unchanged.  Orbit underneath to compare contacts with copper boundaries. These are copper perimeters, not mask or paste apertures. Display artwork does not qualify native model seating, pin 1, electrical behavior or manufacture. The virtual MPN is applied through Adom Chip Laser at the chosen clear package surface described below. See `74LVC2G17GV,125.adom-reference-v3.overlay.json` for source hashes, pose and layer metadata.   ## MPN marking, source and license -**Mark location:** Top cap, along long package axis and offset 0.45 mm toward the blank edge to avoid central manufacturer mark. The exact MPN is a virtual identification inlay generated by `adom-chip-laser`, not a claim about the manufacturer’s actual package marking. The physical source model and reference-artwork geometry remain unchanged.+**Mark location:** Top cap, along long package axis and offset 0.45 mm toward the blank edge to avoid central manufacturer mark. The exact MPN is a virtual identification inlay generated by `adom-chip-laser`, not a claim about the manufacturer’s actual package marking. The physical source model and reference-artwork geometry remain unchanged.  The Source field links to the manufacturer/reference authority. Generation tools such as adom-lbr, adom-symbol, step2glb and Adom Chip Laser are recorded separately in artifact provenance. Original Adom-authored content defaults to the MIT open-source license; manufacturer and upstream assets retain their original terms and attribution. See [license scope](LICENSE-Adom.md). Native CAD parity and manufacturing qualification are separate checks.+++## Cached chip artwork++These reusable chip previews and symbol outlines retain the reviewed Z-up pose and virtual MPN placement. Read the manifest before generating new artwork; compare its source hashes before reuse. Electrical and native model-seating qualification remain separate.++::adom-chip-thumbnail{src="/adom/74lvc2g17gv-125/render/artwork/74LVC2G17GV,125-thumbs.json"}++[Cache manifest and generation recipe](artwork/74LVC2G17GV,125-thumbs.json) · [Original manufacturer STEP](SOT457.step)
page.json+8−1
@@ -44,7 +44,14 @@   "sample_prompts": [],   "discovery_triggers": [],   "discovery_pitch": null,-  "metadata": {},+  "metadata": {+    "chip_thumbnail_cache": {+      "manifest": "artwork/74LVC2G17GV,125-thumbs.json",+      "schema": "adom/chip-artwork-cache@1",+      "widget": "adom-chip-thumbnail",+      "reuse": "Verify source hashes and reuse the reviewed Z-up pose and surface-selected MPN placement."+    }+  },   "created_at": "2026-09-09T21:23:27.062Z",   "updated_at": "2026-09-09T21:23:27.062Z",   "org": "adom"