component
74LVC1G74DC
Public Made by Adomby adom
Nexperia Flip Flops, VSSOP-8-0.5mm. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+116−8@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74lvc1g74dc",+ "title": "74LVC1G74DC",+ "brief": "Nexperia Flip Flops, VSSOP-8-0.5mm. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Flip Flops, VSSOP-8-0.5mm. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74lvc1g74dc" ],+ "component": {+ "mpn": "74LVC1G74DC",+ "manufacturer": "Nexperia",+ "package": "VSSOP-8-0.5mm",+ "pin_count": 8,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74LVC1G74DC.pdf",+ "parts": {+ "symbol": "74lvc1g74dc.kicad_sym",+ "footprint": "74lvc1g74dc.kicad_mod",+ "model_3d": "74lvc1g74dc.glb",+ "model_3d_step": "74lvc1g74dc.step",+ "lbr": "74lvc1g74dc.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "CP",+ "type": "input",+ "description": "Clock input. Positive edge-triggered (LOW-to-HIGH transition) with Schmitt-trigger action; data on D is captured to Q on the rising edge."+ },+ {+ "number": "2",+ "name": "D",+ "type": "input",+ "description": "Data input. Sampled by the flip-flop on the LOW-to-HIGH edge of CP and driven to the Q output when setup/hold requirements are met."+ },+ {+ "number": "3",+ "name": "~Q",+ "type": "output",+ "description": "Complementary (inverted) output. Drives \u00b124 mA at VCC = 3.0 V; complement of Q."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V)."+ },+ {+ "number": "5",+ "name": "Q",+ "type": "output",+ "description": "True output. Drives \u00b124 mA at VCC = 3.0 V; reflects the captured D value after each CP rising edge (subject to SD/RD overrides)."+ },+ {+ "number": "6",+ "name": "~RD",+ "type": "input",+ "description": "Asynchronous reset-direct input, active LOW. Forces Q LOW and ~Q HIGH regardless of CP and D."+ },+ {+ "number": "7",+ "name": "~SD",+ "type": "input",+ "description": "Asynchronous set-direct input, active LOW. Forces Q HIGH and ~Q LOW regardless of CP and D. When both ~SD and ~RD are LOW, both outputs go HIGH."+ },+ {+ "number": "8",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. Recommended operating range 1.65 V to 5.5 V (absolute maximum 6.5 V). Bypass with a local decoupling capacitor."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74LVC1G74DC.pdf",+ "pages": 19,+ "sha256": "a601aca999c05cc2",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "VSSOP-8-0.5mm",+ "Category": "Logic",+ "Pins": "8"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74lvc1g74dc"+ ],+ "discovery_pitch": "74LVC1G74DC (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/74lvc1g74dc-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }