74lv132at14-13: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC b…
74lv132at14-13: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
74lv132at14-13: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero
74lv132at14-13: laser-etched CAD + chip hero (factory 2.0.0 backfill)
Brief states the pinout check that actually ran (was an unconditional "Datasheet-verified pinout")
74lv132at14-13: hero re-rendered with iso-front (part number upright)
74lv132at14-13: laser-etched CAD + chip hero (factory 2.0.0 backfill)
74lv132at14-13: stamp component.logic (74LV132) from component-ocean
74lv132at14-13: factory component page (tier=lcsc)
Initial commit: component/74lv132at14-13