74HCT595D

@@ -0,0 +1,58 @@+# 74HCT595D++**Nexperia** · Shifting Register · SOIC-16++74HCT595D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Q1 | tri_state | Parallel data output 1. 3-state output from the storage register; high-impedance when OE is HIGH. Bus driver output rated approximately 6 mA at VCC = 4.5 V. |+| 2 | Q2 | tri_state | Parallel data output 2. 3-state output from the storage register; high-impedance when OE is HIGH. |+| 3 | Q3 | tri_state | Parallel data output 3. 3-state output from the storage register; high-impedance when OE is HIGH. |+| 4 | Q4 | tri_state | Parallel data output 4. 3-state output from the storage register; high-impedance when OE is HIGH. |+| 5 | Q5 | tri_state | Parallel data output 5. 3-state output from the storage register; high-impedance when OE is HIGH. |+| 6 | Q6 | tri_state | Parallel data output 6. 3-state output from the storage register; high-impedance when OE is HIGH. |+| 7 | Q7 | tri_state | Parallel data output 7 (MSB of the storage register). 3-state output; high-impedance when OE is HIGH. |+| 8 | GND | power_in | Ground reference (0 V). Max ground current 70 mA. |+| 9 | Q7S | output | Serial data output. Provides the Q6S contents of the shift register (one clock ahead of Q7) to enable cascading multiple 595s. Rated approximately 4 mA at VCC = 4.5 V; not 3-state (always active). |+| 10 | MR | input | Master reset, active LOW. Asynchronously clears the shift register only; does not affect the storage register or parallel outputs directly. TTL-compatible input. |+| 11 | SHCP | input | Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Typical fmax ~91 MHz at VCC = 4.5 V. |+| 12 | STCP | input | Storage register clock input (latch clock). On the LOW-to-HIGH transition, the contents of the shift register are transferred to the 8-bit storage register (parallel output latch). |+| 13 | OE | input | Output enable, active LOW. When LOW, storage register contents appear on Q0-Q7; when HIGH, the parallel outputs enter high-impedance OFF-state. Does not affect the shift or storage register state. |+| 14 | DS | input | Serial data input. Sampled by the shift register on the rising edge of SHCP. TTL-compatible input. |+| 15 | Q0 | tri_state | Parallel data output 0 (LSB of the storage register). 3-state output; high-impedance when OE is HIGH. |+| 16 | VCC | power_in | Supply voltage. Operating range 4.5 V to 5.5 V for 74HCT595 (JESD8C compliant). Absolute maximum -0.5 V to +7 V. Typical ICC ~80 uA at VCC = 5.5 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `74HCT595DD`+- `74HCT595DPW`+- `74HCT595DBQ`+- `74HCT595DBZ`++## CAD (KiCad official)++- Symbol: `74HCT595D`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HCT595D.pdf) (21 pp, sha256 `fa24207e780cd8c4`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hct595d-datasheet.pdf)

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