component
74HCT595D
Public Made by Adomby adom
Nexperia Shifting Register, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+507−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/74hct595d-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+505@@ -0,0 +1,505 @@+{+ "schema": "adom.pads/1",+ "slug": "74hct595d",+ "footprint": "SOIC-16_3.9x9.9mm_P1.27mm",+ "generated_from": {+ "footprint": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.475,+ -4.445+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c"+ },+ "pad_count": 16,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "Q1",+ "type": "tri_state",+ "description": "Parallel data output 1. 3-state output from the storage register; high-impedance when OE is HIGH. Bus driver output rated approximately 6 mA at VCC = 4.5 V.",+ "is_pin1": true,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "Q2",+ "type": "tri_state",+ "description": "Parallel data output 2. 3-state output from the storage register; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "Q3",+ "type": "tri_state",+ "description": "Parallel data output 3. 3-state output from the storage register; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "Q4",+ "type": "tri_state",+ "description": "Parallel data output 4. 3-state output from the storage register; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "Q5",+ "type": "tri_state",+ "description": "Parallel data output 5. 3-state output from the storage register; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "Q6",+ "type": "tri_state",+ "description": "Parallel data output 6. 3-state output from the storage register; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "Q7",+ "type": "tri_state",+ "description": "Parallel data output 7 (MSB of the storage register). 3-state output; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.475,+ 4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Max ground current 70 mA.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "9",+ "name": "Q7S",+ "type": "output",+ "description": "Serial data output. Provides the Q6S contents of the shift register (one clock ahead of Q7) to enable cascading multiple 595s. Rated approximately 4 mA at VCC = 4.5 V; not 3-state (always active).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "10",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "10",+ "name": "MR",+ "type": "input",+ "description": "Master reset, active LOW. Asynchronously clears the shift register only; does not affect the storage register or parallel outputs directly. TTL-compatible input.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "11",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "11",+ "name": "SHCP",+ "type": "input",+ "description": "Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Typical fmax ~91 MHz at VCC = 4.5 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "12",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ 0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "12",+ "name": "STCP",+ "type": "input",+ "description": "Storage register clock input (latch clock). On the LOW-to-HIGH transition, the contents of the shift register are transferred to the 8-bit storage register (parallel output latch).",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "13",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -0.635+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "13",+ "name": "OE",+ "type": "input",+ "description": "Output enable, active LOW. When LOW, storage register contents appear on Q0-Q7; when HIGH, the parallel outputs enter high-impedance OFF-state. Does not affect the shift or storage register state.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "14",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -1.905+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "14",+ "name": "DS",+ "type": "input",+ "description": "Serial data input. Sampled by the shift register on the rising edge of SHCP. TTL-compatible input.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "15",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -3.175+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "15",+ "name": "Q0",+ "type": "tri_state",+ "description": "Parallel data output 0 (LSB of the storage register). 3-state output; high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "16",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.475,+ -4.445+ ],+ "rot": 0.0,+ "size": [+ 1.95,+ 0.6+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. Operating range 4.5 V to 5.5 V for 74HCT595 (JESD8C compliant). Absolute maximum -0.5 V to +7 V. Typical ICC ~80 uA at VCC = 5.5 V.",+ "is_pin1": false,+ "source": {+ "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}