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Initial commit: component/74hc86d

Ray ·e84dd21389 ·2mo ago
2 files changed +88
README.mdadded+54
@@ -0,0 +1,54 @@+# 74HC86D++**Nexperia** · Gates · SOIC-14++74HC86D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Gate 1 data input A. CMOS-level logic input to the first 2-input XOR gate. |+| 2 | 1B | input | Gate 1 data input B. CMOS-level logic input to the first 2-input XOR gate. |+| 3 | 1Y | output | Gate 1 data output. XOR result of inputs 1A and 1B. Drives up to ±5.2 mA at VCC = 6.0 V. |+| 4 | 2A | input | Gate 2 data input A. CMOS-level logic input to the second 2-input XOR gate. |+| 5 | 2B | input | Gate 2 data input B. CMOS-level logic input to the second 2-input XOR gate. |+| 6 | 2Y | output | Gate 2 data output. XOR result of inputs 2A and 2B. Drives up to ±5.2 mA at VCC = 6.0 V. |+| 7 | GND | power_in | Ground reference (0 V). Common return for supply and all logic signals. |+| 8 | 3Y | output | Gate 3 data output. XOR result of inputs 3A and 3B. Drives up to ±5.2 mA at VCC = 6.0 V. |+| 9 | 3A | input | Gate 3 data input A. CMOS-level logic input to the third 2-input XOR gate. |+| 10 | 3B | input | Gate 3 data input B. CMOS-level logic input to the third 2-input XOR gate. |+| 11 | 4Y | output | Gate 4 data output. XOR result of inputs 4A and 4B. Drives up to ±5.2 mA at VCC = 6.0 V. |+| 12 | 4A | input | Gate 4 data input A. CMOS-level logic input to the fourth 2-input XOR gate. |+| 13 | 4B | input | Gate 4 data input B. CMOS-level logic input to the fourth 2-input XOR gate. |+| 14 | VCC | power_in | Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC86) or 4.5 V to 5.5 V (74HCT86). Bypass with a 100 nF ceramic capacitor to GND close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `74HC86DD`+- `74HC86DPW`++## CAD (KiCad official)++- Symbol: `74HC86D`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC86D.pdf) (12 pp, sha256 `efb3cf17b91fff76`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc86d-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "74hc86d",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "74hc86d"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "74hc86d.kicad_sym",+    "74hc86d.kicad_mod",+    "74hc86d.glb",+    "74hc86d.step",+    "74hc86d.lbr",+    "docs/hero.png",+    "docs/74hc86d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file