component
74HC595PW
Public Made by Adomby adom
Nexperia Shifting Register, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+507−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/74hc595pw-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+505@@ -0,0 +1,505 @@+{+ "schema": "adom.pads/1",+ "slug": "74hc595pw",+ "footprint": "TSSOP-16_4.4x5mm_P0.65mm",+ "generated_from": {+ "footprint": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.8625,+ -2.275+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "TSSOP-16_4.4x5mm_P0.65mm@sha256:fbac79fc5f310754"+ },+ "pad_count": 16,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -2.275+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "Q1",+ "type": "output",+ "description": "Parallel data output bit 1 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH. Bus driver output: sourcing/sinking up to ~6 mA at VCC = 4.5 V.",+ "is_pin1": true,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -1.625+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "Q2",+ "type": "output",+ "description": "Parallel data output bit 2 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -0.975+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "Q3",+ "type": "output",+ "description": "Parallel data output bit 3 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -0.325+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "Q4",+ "type": "output",+ "description": "Parallel data output bit 4 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 0.325+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "Q5",+ "type": "output",+ "description": "Parallel data output bit 5 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 0.975+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "Q6",+ "type": "output",+ "description": "Parallel data output bit 6 from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 1.625+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "Q7",+ "type": "output",+ "description": "Parallel data output bit 7 (MSB) from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 2.275+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Connect to system ground.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 2.275+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "9",+ "name": "Q7S",+ "type": "output",+ "description": "Serial data output from the last stage of the shift register. Used to cascade multiple 74HC595 devices by tying to the next stage's DS input. Non-3-state; drives up to ~4 mA at VCC = 4.5 V.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "10",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 1.625+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "10",+ "name": "MR",+ "type": "input",+ "description": "Master reset input, active LOW. A LOW level asynchronously clears the shift register (does not affect the storage register/parallel outputs). Must be held HIGH during normal shift operation.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "11",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 0.975+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "11",+ "name": "SHCP",+ "type": "input",+ "description": "Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP. Equivalent to the SPI SCK for the shift stage; typical max frequency ~100 MHz at VCC = 6 V.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "12",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 0.325+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "12",+ "name": "STCP",+ "type": "input",+ "description": "Storage register clock input (latch). On the LOW-to-HIGH transition of STCP, the contents of the shift register are transferred to the storage register and appear on Q0..Q7. Commonly called the 'latch' or 'RCK' pin.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "13",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -0.325+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "13",+ "name": "OE",+ "type": "input",+ "description": "Output enable input, active LOW. LOW enables the Q0..Q7 parallel outputs; HIGH forces Q0..Q7 to a high-impedance OFF-state. Does not affect the state of the shift or storage registers.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "14",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -0.975+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "14",+ "name": "DS",+ "type": "input",+ "description": "Serial data input. Sampled into shift register stage 0 on the LOW-to-HIGH edge of SHCP. Equivalent to SPI MOSI for cascaded shift-register chains.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "15",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -1.625+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "15",+ "name": "Q0",+ "type": "output",+ "description": "Parallel data output bit 0 (LSB) from the storage register. 3-state; driven when OE is LOW, high-impedance when OE is HIGH.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "16",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -2.275+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 2.0 V to 6.0 V (74HC595) / 4.5 V to 5.5 V (74HCT595). Absolute maximum 7 V. Decouple locally with a 100 nF ceramic capacitor to GND.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-16_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}