74HC595M

@@ -0,0 +1,58 @@+# 74HC595M++**HGSEMI** · Shifting Register · SOP-16++74HC595M from HGSEMI, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | QB | tri_state | Parallel data output bit B. Tri-state; enabled when /G is low, high-Z when /G is high. Reflects the stored value in the output storage register. |+| 2 | QC | tri_state | Parallel data output bit C. Tri-state; enabled when /G is low, high-Z when /G is high. |+| 3 | QD | tri_state | Parallel data output bit D. Tri-state; enabled when /G is low, high-Z when /G is high. |+| 4 | QE | tri_state | Parallel data output bit E. Tri-state; enabled when /G is low, high-Z when /G is high. |+| 5 | QF | tri_state | Parallel data output bit F. Tri-state; enabled when /G is low, high-Z when /G is high. |+| 6 | QG | tri_state | Parallel data output bit G. Tri-state; enabled when /G is low, high-Z when /G is high. |+| 7 | QH | tri_state | Parallel data output bit H (MSB of the 8-bit storage register). Tri-state; enabled when /G is low, high-Z when /G is high. |+| 8 | GND | power_in | Ground reference (0 V). Return for VCC. |+| 9 | Q'H | output | Serial data output from the last stage (QH) of the shift register. Used to cascade multiple 74HC595 devices to form an 8n-bit shift register. Not tri-stated by /G. |+| 10 | /SCLR | input | Active-low shift register clear. When held low, the 8-bit shift register is asynchronously reset to zero. Must be held high for normal shift operation. |+| 11 | SCK | input | Shift register clock. Serial data on SER is sampled and shifted through the 8-bit register on the rising edge of SCK. Maximum frequency 10 MHz (typ, VCC=5V). |+| 12 | RCK | input | Storage (latch) register clock. On the rising edge of RCK, the current contents of the shift register are transferred to the 8-bit output storage register and appear at QA..QH. |+| 13 | /G | input | Active-low output enable for the parallel outputs QA..QH. When low, outputs are driven; when high, QA..QH are placed in high-impedance (tri-state). Does not affect Q'H or the internal registers. |+| 14 | SER | input | Serial data input. The logic level on SER is loaded into the first stage of the shift register on the rising edge of SCK. |+| 15 | QA | tri_state | Parallel data output bit A (LSB of the 8-bit storage register). Tri-state; enabled when /G is low, high-Z when /G is high. |+| 16 | VCC | power_in | Positive supply voltage. Operating range 3.2 V to 6 V (typ 5 V); absolute max 6.5 V. Bypass with a local 0.1 µF ceramic capacitor to GND. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HGSEMI |+| Package | SOP-16 |+| Category | Logic |+| Pins | 16 |++## Ordering variants++- `74HC595MM/TR`+- `74HC595MN`+- `74HC595MMT/TR`+- `74HC595MLQ/TR`++## CAD (KiCad official)++- Symbol: `74HC595M`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HGSEMI datasheet](docs/74hc595m-datasheet.pdf) (13 pp, sha256 `2466d95b2f765594`, retrieved 2026-08-17, tier: lcsc)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc595m-datasheet.pdf)

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