component
74HC595D
Public Made by Adomby adom
JSMSEMI LED Display Drivers, SOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74hc595d",+ "title": "74HC595D",+ "brief": "Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Shifting Register, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74hc595d" ],+ "component": {+ "mpn": "74HC595D",+ "manufacturer": "Nexperia",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shifting Register",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC595D.pdf",+ "parts": {+ "symbol": "74hc595d.kicad_sym",+ "footprint": "74hc595d.kicad_mod",+ "model_3d": "74hc595d.glb",+ "model_3d_step": "74hc595d.step",+ "lbr": "74hc595d.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Q1",+ "type": "output",+ "description": "Parallel data output bit 1 from the 8-bit storage register. 3-state output; goes to high-impedance when OE is HIGH. Drive capability approximately \u00b16 mA at VCC = 4.5 V."+ },+ {+ "number": "2",+ "name": "Q2",+ "type": "output",+ "description": "Parallel data output bit 2 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "3",+ "name": "Q3",+ "type": "output",+ "description": "Parallel data output bit 3 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "4",+ "name": "Q4",+ "type": "output",+ "description": "Parallel data output bit 4 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "5",+ "name": "Q5",+ "type": "output",+ "description": "Parallel data output bit 5 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "6",+ "name": "Q6",+ "type": "output",+ "description": "Parallel data output bit 6 from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "7",+ "name": "Q7",+ "type": "output",+ "description": "Parallel data output bit 7 (MSB) from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V)."+ },+ {+ "number": "9",+ "name": "Q7S",+ "type": "output",+ "description": "Serial data output tapped from the last stage of the shift register (not 3-state); used to cascade multiple 74HC595 devices. Drive capability approximately \u00b14 mA at VCC = 4.5 V."+ },+ {+ "number": "10",+ "name": "MR",+ "type": "input",+ "description": "Master reset, active LOW. Asynchronously clears the 8-bit shift register only (does not clear the storage register). Must be held HIGH during normal shifting."+ },+ {+ "number": "11",+ "name": "SHCP",+ "type": "input",+ "description": "Shift register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition of SHCP."+ },+ {+ "number": "12",+ "name": "STCP",+ "type": "input",+ "description": "Storage register clock (latch) input. On the LOW-to-HIGH transition, the contents of the shift register are transferred to the 8-bit storage register (parallel outputs)."+ },+ {+ "number": "13",+ "name": "OE",+ "type": "input",+ "description": "Output enable, active LOW. When HIGH, parallel outputs Q0..Q7 go to high-impedance OFF-state. Does not affect Q7S or the register contents."+ },+ {+ "number": "14",+ "name": "DS",+ "type": "input",+ "description": "Serial data input. Sampled on the LOW-to-HIGH transition of SHCP and shifted into stage 0 of the shift register."+ },+ {+ "number": "15",+ "name": "Q0",+ "type": "output",+ "description": "Parallel data output bit 0 (LSB) from the 8-bit storage register. 3-state output; high-impedance when OE is HIGH."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. Operating range 2.0 V to 6.0 V (74HC595); recommended typical 5.0 V. Bypass with a 100 nF ceramic capacitor to GND close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74HC595D.pdf",+ "pages": 21,+ "sha256": "fa24207e780cd8c4",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "SOIC-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74hc595d"+ ],+ "discovery_pitch": "74HC595D (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/74hc595d-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }