74HC573PW

@@ -0,0 +1,61 @@+# 74HC573PW++**Nexperia** · Latches · TSSOP-20++74HC573PW from Nexperia, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | OE | input | 3-state output enable input, active LOW. When HIGH the Q0..Q7 outputs are forced to the high-impedance OFF-state; latch contents are unaffected. CMOS-level input (TTL-level on 74HCT573PW). |+| 2 | D0 | input | Data input bit 0. Captured into latch 1 on the HIGH-to-LOW transition of LE. Input includes clamp diodes allowing current-limited interfacing above VCC. |+| 3 | D1 | input | Data input bit 1. Captured into latch 2 on the HIGH-to-LOW transition of LE. |+| 4 | D2 | input | Data input bit 2. Captured into latch 3 on the HIGH-to-LOW transition of LE. |+| 5 | D3 | input | Data input bit 3. Captured into latch 4 on the HIGH-to-LOW transition of LE. |+| 6 | D4 | input | Data input bit 4. Captured into latch 5 on the HIGH-to-LOW transition of LE. |+| 7 | D5 | input | Data input bit 5. Captured into latch 6 on the HIGH-to-LOW transition of LE. |+| 8 | D6 | input | Data input bit 6. Captured into latch 7 on the HIGH-to-LOW transition of LE. |+| 9 | D7 | input | Data input bit 7. Captured into latch 8 on the HIGH-to-LOW transition of LE. |+| 10 | GND | power_in | Ground reference, 0 V. |+| 11 | LE | input | Latch enable input, active HIGH. While LE is HIGH the latches are transparent (Qn follows Dn); on the HIGH-to-LOW transition the input data is stored. |+| 12 | Q7 | tri_state | 3-state non-inverting latch output bit 7. Reflects stored D7 when OE is LOW; high-impedance when OE is HIGH. Drives ±6 mA at VCC=4.5 V. |+| 13 | Q6 | tri_state | 3-state non-inverting latch output bit 6. Reflects stored D6 when OE is LOW; high-impedance when OE is HIGH. |+| 14 | Q5 | tri_state | 3-state non-inverting latch output bit 5. Reflects stored D5 when OE is LOW; high-impedance when OE is HIGH. |+| 15 | Q4 | tri_state | 3-state non-inverting latch output bit 4. Reflects stored D4 when OE is LOW; high-impedance when OE is HIGH. |+| 16 | Q3 | tri_state | 3-state non-inverting latch output bit 3. Reflects stored D3 when OE is LOW; high-impedance when OE is HIGH. |+| 17 | Q2 | tri_state | 3-state non-inverting latch output bit 2. Reflects stored D2 when OE is LOW; high-impedance when OE is HIGH. |+| 18 | Q1 | tri_state | 3-state non-inverting latch output bit 1. Reflects stored D1 when OE is LOW; high-impedance when OE is HIGH. |+| 19 | Q0 | tri_state | 3-state non-inverting latch output bit 0. Reflects stored D0 when OE is LOW; high-impedance when OE is HIGH. |+| 20 | VCC | power_in | Supply voltage. 2.0 V to 6.0 V for 74HC573; 4.5 V to 5.5 V for 74HCT573. Absolute maximum 7 V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | TSSOP-20 |+| Category | Logic |+| Pins | 20 |++## Ordering variants++- `74HC573PWPW`+- `74HC573PWD`+- `74HC573PWBQ`++## CAD (KiCad official)++- Symbol: `74HC573PW`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC573PW.pdf) (16 pp, sha256 `2feaa6991e6dc5d6`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc573pw-datasheet.pdf)

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