component
74HC573PW
Public Made by Adomby adom
Nexperia Latches, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+188−8@@ -1,13 +1,198 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74hc573pw",+ "title": "74HC573PW",+ "brief": "Nexperia Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Latches, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74hc573pw" ],+ "component": {+ "mpn": "74HC573PW",+ "manufacturer": "Nexperia",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Latches",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC573PW.pdf",+ "parts": {+ "symbol": "74hc573pw.kicad_sym",+ "footprint": "74hc573pw.kicad_mod",+ "model_3d": "74hc573pw.glb",+ "model_3d_step": "74hc573pw.step",+ "lbr": "74hc573pw.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "OE",+ "type": "input",+ "description": "3-state output enable input, active LOW. When HIGH the Q0..Q7 outputs are forced to the high-impedance OFF-state; latch contents are unaffected. CMOS-level input (TTL-level on 74HCT573PW)."+ },+ {+ "number": "2",+ "name": "D0",+ "type": "input",+ "description": "Data input bit 0. Captured into latch 1 on the HIGH-to-LOW transition of LE. Input includes clamp diodes allowing current-limited interfacing above VCC."+ },+ {+ "number": "3",+ "name": "D1",+ "type": "input",+ "description": "Data input bit 1. Captured into latch 2 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "4",+ "name": "D2",+ "type": "input",+ "description": "Data input bit 2. Captured into latch 3 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "5",+ "name": "D3",+ "type": "input",+ "description": "Data input bit 3. Captured into latch 4 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "6",+ "name": "D4",+ "type": "input",+ "description": "Data input bit 4. Captured into latch 5 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "7",+ "name": "D5",+ "type": "input",+ "description": "Data input bit 5. Captured into latch 6 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "8",+ "name": "D6",+ "type": "input",+ "description": "Data input bit 6. Captured into latch 7 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "9",+ "name": "D7",+ "type": "input",+ "description": "Data input bit 7. Captured into latch 8 on the HIGH-to-LOW transition of LE."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, 0 V."+ },+ {+ "number": "11",+ "name": "LE",+ "type": "input",+ "description": "Latch enable input, active HIGH. While LE is HIGH the latches are transparent (Qn follows Dn); on the HIGH-to-LOW transition the input data is stored."+ },+ {+ "number": "12",+ "name": "Q7",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 7. Reflects stored D7 when OE is LOW; high-impedance when OE is HIGH. Drives \u00b16 mA at VCC=4.5 V."+ },+ {+ "number": "13",+ "name": "Q6",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 6. Reflects stored D6 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "14",+ "name": "Q5",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 5. Reflects stored D5 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "15",+ "name": "Q4",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 4. Reflects stored D4 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "16",+ "name": "Q3",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 3. Reflects stored D3 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "17",+ "name": "Q2",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 2. Reflects stored D2 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "18",+ "name": "Q1",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 1. Reflects stored D1 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "19",+ "name": "Q0",+ "type": "tri_state",+ "description": "3-state non-inverting latch output bit 0. Reflects stored D0 when OE is LOW; high-impedance when OE is HIGH."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. 2.0 V to 6.0 V for 74HC573; 4.5 V to 5.5 V for 74HCT573. Absolute maximum 7 V."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74HC573PW.pdf",+ "pages": 16,+ "sha256": "2feaa6991e6dc5d6",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "TSSOP-20",+ "Category": "Logic",+ "Pins": "20"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74hc573pw"+ ],+ "discovery_pitch": "74HC573PW (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +210,5 @@ "docs/74hc573pw-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }