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74HC4094D
Public Made by Adomby adom
Nexperia Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+51@@ -0,0 +1,51 @@+# 74HC4094D++**Nexperia** · Shift Registers · SOIC-16++74HC4094D from Nexperia, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | STR | input | Strobe input; data in shift register is transferred to storage register when STR input is HIGH. |+| 2 | D | input | Serial data input to the 8-stage shift register. |+| 3 | CP | input | Clock input; data is shifted on LOW-to-HIGH transitions of CP input. |+| 4 | QP0 | tri_state | Parallel output (stage 0) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 5 | QP1 | tri_state | Parallel output (stage 1) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 6 | QP2 | tri_state | Parallel output (stage 2) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 7 | QP3 | tri_state | Parallel output (stage 3) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 8 | GND | power_in | Ground supply voltage (0 V reference). |+| 9 | QS1 | tri_state | Serial output; data is available on LOW-to-HIGH transitions of CP for cascading with fast clock edges. |+| 10 | QS2 | tri_state | Serial output; data is available on next HIGH-to-LOW transition of CP for cascading with slow clock edges. |+| 11 | QP7 | tri_state | Parallel output (stage 7) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 12 | QP6 | tri_state | Parallel output (stage 6) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 13 | QP5 | tri_state | Parallel output (stage 5) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 14 | QP4 | tri_state | Parallel output (stage 4) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW. |+| 15 | OE | input | Output enable input; HIGH enables outputs, LOW causes high-impedance OFF-state; does not affect register state. |+| 16 | VCC | power_in | Supply voltage for 74HC4094; recommended range 2.0 to 6.0 V, operating temperature -40 to +125 °C. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `74HC4094D`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579711935807750144) (19 pp, sha256 `a8d541aff709a8db`, retrieved 2026-09-17, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc4094d-datasheet.pdf)
page.jsonadded+186@@ -0,0 +1,186 @@+{+ "slug": "74hc4094d",+ "version": "0.1.0",+ "type": "component",+ "description": "Nexperia Shift Registers, SOIC-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "74hc4094d",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "74hc4094d.kicad_sym",+ "74hc4094d.kicad_mod",+ "74hc4094d.glb",+ "74hc4094d.step",+ "74hc4094d.lbr",+ "docs/hero.png",+ "docs/74hc4094d-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "74HC4094D",+ "manufacturer": "Nexperia",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579711935807750144",+ "parts": {+ "symbol": "74hc4094d.kicad_sym",+ "footprint": "74hc4094d.kicad_mod",+ "model_3d": "74hc4094d.glb",+ "model_3d_step": "74hc4094d.step",+ "lbr": "74hc4094d.lbr"+ },+ "distributor_links": {+ "lcsc": "C5651"+ },+ "pins": [+ {+ "number": "1",+ "name": "STR",+ "type": "input",+ "description": "Strobe input; data in shift register is transferred to storage register when STR input is HIGH."+ },+ {+ "number": "2",+ "name": "D",+ "type": "input",+ "description": "Serial data input to the 8-stage shift register."+ },+ {+ "number": "3",+ "name": "CP",+ "type": "input",+ "description": "Clock input; data is shifted on LOW-to-HIGH transitions of CP input."+ },+ {+ "number": "4",+ "name": "QP0",+ "type": "tri_state",+ "description": "Parallel output (stage 0) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "5",+ "name": "QP1",+ "type": "tri_state",+ "description": "Parallel output (stage 1) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "6",+ "name": "QP2",+ "type": "tri_state",+ "description": "Parallel output (stage 2) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "7",+ "name": "QP3",+ "type": "tri_state",+ "description": "Parallel output (stage 3) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground supply voltage (0 V reference)."+ },+ {+ "number": "9",+ "name": "QS1",+ "type": "tri_state",+ "description": "Serial output; data is available on LOW-to-HIGH transitions of CP for cascading with fast clock edges."+ },+ {+ "number": "10",+ "name": "QS2",+ "type": "tri_state",+ "description": "Serial output; data is available on next HIGH-to-LOW transition of CP for cascading with slow clock edges."+ },+ {+ "number": "11",+ "name": "QP7",+ "type": "tri_state",+ "description": "Parallel output (stage 7) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "12",+ "name": "QP6",+ "type": "tri_state",+ "description": "Parallel output (stage 6) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "13",+ "name": "QP5",+ "type": "tri_state",+ "description": "Parallel output (stage 5) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "14",+ "name": "QP4",+ "type": "tri_state",+ "description": "Parallel output (stage 4) with 3-state capability; data appears when OE is HIGH, HIGH impedance when OE is LOW."+ },+ {+ "number": "15",+ "name": "OE",+ "type": "input",+ "description": "Output enable input; HIGH enables outputs, LOW causes high-impedance OFF-state; does not affect register state."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage for 74HC4094; recommended range 2.0 to 6.0 V, operating temperature -40 to +125 °C."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 19,+ "cost_usd": 0.1988,+ "at": "2026-09-17T17:53:14"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8579711935807750144",+ "pages": 19,+ "sha256": "a8d541aff709a8db",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}