component
74HC4052MT
Public Made by Adomby adom
HGSEMI Analog Switches / Multiplexers, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+164−8@@ -1,13 +1,174 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74hc4052mt",+ "title": "74HC4052MT",+ "brief": "HGSEMI Analog Switches / Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "HGSEMI Analog Switches / Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "comm-uart", "74hc4052mt" ],+ "component": {+ "mpn": "74HC4052MT",+ "manufacturer": "HGSEMI",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Comm/UART",+ "subcategory": "Analog Switches / Multiplexers",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2206141530_HGSEMI-74HC4052MT-TR_C3007955.pdf",+ "parts": {+ "symbol": "74hc4052mt.kicad_sym",+ "footprint": "74hc4052mt.kicad_mod",+ "model_3d": "74hc4052mt.glb",+ "model_3d_step": "74hc4052mt.step",+ "lbr": "74hc4052mt.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Y0B",+ "type": "bidirectional",+ "description": "Bank B independent input/output channel 0. Connects to ZB when A1=L, A0=L and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "2",+ "name": "Y2B",+ "type": "bidirectional",+ "description": "Bank B independent input/output channel 2. Connects to ZB when A1=H, A0=L and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "3",+ "name": "ZB",+ "type": "bidirectional",+ "description": "Bank B common input/output. Routed to the selected Y0B-Y3B channel when E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "4",+ "name": "Y3B",+ "type": "bidirectional",+ "description": "Bank B independent input/output channel 3. Connects to ZB when A1=H, A0=H and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "5",+ "name": "Y1B",+ "type": "bidirectional",+ "description": "Bank B independent input/output channel 1. Connects to ZB when A1=L, A0=H and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "6",+ "name": "E",+ "type": "input",+ "description": "Active-low enable input. When E=L the mux passes signals per A0/A1; when E=H all channels are in a high-impedance off state (IOZY typ. <200 nA)."+ },+ {+ "number": "7",+ "name": "VEE",+ "type": "power_in",+ "description": "Negative analog supply for the switch pass-transistors, sets the lower limit of the analog signal range. Recommended VEE = -6.0 V to 0 V; for pure digital-mux use tie VEE to VSS (GND)."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground / digital return for the A0, A1, E logic inputs."+ },+ {+ "number": "9",+ "name": "A1",+ "type": "input",+ "description": "Digital select input, bit 1 (MSB) of the 2-bit channel-select code for both banks. Referenced to VDD/VSS."+ },+ {+ "number": "10",+ "name": "A0",+ "type": "input",+ "description": "Digital select input, bit 0 (LSB) of the 2-bit channel-select code for both banks. Referenced to VDD/VSS."+ },+ {+ "number": "11",+ "name": "Y3A",+ "type": "bidirectional",+ "description": "Bank A independent input/output channel 3. Connects to ZA when A1=H, A0=H and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "12",+ "name": "Y0A",+ "type": "bidirectional",+ "description": "Bank A independent input/output channel 0. Connects to ZA when A1=L, A0=L and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "13",+ "name": "ZA",+ "type": "bidirectional",+ "description": "Bank A common input/output. Routed to the selected Y0A-Y3A channel when E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "14",+ "name": "Y1A",+ "type": "bidirectional",+ "description": "Bank A independent input/output channel 1. Connects to ZA when A1=L, A0=H and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "15",+ "name": "Y2A",+ "type": "bidirectional",+ "description": "Bank A independent input/output channel 2. Connects to ZA when A1=H, A0=L and E=L. Analog signal range VEE to VDD."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply for the digital control logic and upper analog rail. Recommended VDD = 3.0 V to 9.0 V (5.0 V typical); VDD-VEE must not exceed 9 V (12 V absolute max)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2206141530_HGSEMI-74HC4052MT-TR_C3007955.pdf",+ "pages": 13,+ "sha256": "c10511caf4ff602c",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "HGSEMI",+ "Package": "TSSOP-16",+ "Category": "Comm/UART",+ "Pins": "16"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74hc4052mt"+ ],+ "discovery_pitch": "74HC4052MT (HGSEMI) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +186,5 @@ "docs/74hc4052mt-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }