74HC4052MT

@@ -0,0 +1,60 @@+# 74HC4052MT++**HGSEMI** · Analog Switches / Multiplexers · TSSOP-16++74HC4052MT from HGSEMI, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | Y0B | bidirectional | Bank B independent input/output channel 0. Connects to ZB when A1=L, A0=L and E=L. Analog signal range VEE to VDD. |+| 2 | Y2B | bidirectional | Bank B independent input/output channel 2. Connects to ZB when A1=H, A0=L and E=L. Analog signal range VEE to VDD. |+| 3 | ZB | bidirectional | Bank B common input/output. Routed to the selected Y0B-Y3B channel when E=L. Analog signal range VEE to VDD. |+| 4 | Y3B | bidirectional | Bank B independent input/output channel 3. Connects to ZB when A1=H, A0=H and E=L. Analog signal range VEE to VDD. |+| 5 | Y1B | bidirectional | Bank B independent input/output channel 1. Connects to ZB when A1=L, A0=H and E=L. Analog signal range VEE to VDD. |+| 6 | E | input | Active-low enable input. When E=L the mux passes signals per A0/A1; when E=H all channels are in a high-impedance off state (IOZY typ. <200 nA). |+| 7 | VEE | power_in | Negative analog supply for the switch pass-transistors, sets the lower limit of the analog signal range. Recommended VEE = -6.0 V to 0 V; for pure digital-mux use tie VEE to VSS (GND). |+| 8 | VSS | power_in | Ground / digital return for the A0, A1, E logic inputs. |+| 9 | A1 | input | Digital select input, bit 1 (MSB) of the 2-bit channel-select code for both banks. Referenced to VDD/VSS. |+| 10 | A0 | input | Digital select input, bit 0 (LSB) of the 2-bit channel-select code for both banks. Referenced to VDD/VSS. |+| 11 | Y3A | bidirectional | Bank A independent input/output channel 3. Connects to ZA when A1=H, A0=H and E=L. Analog signal range VEE to VDD. |+| 12 | Y0A | bidirectional | Bank A independent input/output channel 0. Connects to ZA when A1=L, A0=L and E=L. Analog signal range VEE to VDD. |+| 13 | ZA | bidirectional | Bank A common input/output. Routed to the selected Y0A-Y3A channel when E=L. Analog signal range VEE to VDD. |+| 14 | Y1A | bidirectional | Bank A independent input/output channel 1. Connects to ZA when A1=L, A0=H and E=L. Analog signal range VEE to VDD. |+| 15 | Y2A | bidirectional | Bank A independent input/output channel 2. Connects to ZA when A1=H, A0=L and E=L. Analog signal range VEE to VDD. |+| 16 | VDD | power_in | Positive supply for the digital control logic and upper analog rail. Recommended VDD = 3.0 V to 9.0 V (5.0 V typical); VDD-VEE must not exceed 9 V (12 V absolute max). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | HGSEMI |+| Package | TSSOP-16 |+| Category | Comm/UART |+| Pins | 16 |++## Ordering variants++- `74HC4052MT/TR`+- `74HC4052MTN`+- `74HC4052MTM/TR`+- `74HC4052MTMS/TR`+- `74HC4052MTLQ/TR`++## CAD (KiCad official)++- Symbol: `74HC4052MT`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [HGSEMI datasheet](docs/74hc4052mt-datasheet.pdf) (13 pp, sha256 `c10511caf4ff602c`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc4052mt-datasheet.pdf)

@@ -0,0 +1,34 @@+{+  "slug": "74hc4052mt",+  "version": "0.1.0",+  "type": "component",+  "description": "HGSEMI Analog Switches / Multiplexers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "comm-uart",+    "74hc4052mt"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "74hc4052mt.kicad_sym",+    "74hc4052mt.kicad_mod",+    "74hc4052mt.glb",+    "74hc4052mt.step",+    "74hc4052mt.lbr",+    "docs/hero.png",+    "docs/74hc4052mt-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file