74hc32s

@@ -0,0 +1,55 @@+# 74HC32S++**GR** · Gates · SOP-14++74HC32S from GR, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A1 | input | Gate 1 input A. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 2 | B1 | input | Gate 1 input B. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 3 | Y1 | output | Gate 1 output, Y1 = A1 + B1. Push-pull CMOS output; drives ≤ 4.0 mA at VCC = 4.5 V with VOH ≥ 3.7 V and VOL ≤ 0.4 V. Max per-pin IOUT ±25 mA. |+| 4 | A2 | input | Gate 2 input A. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 5 | B2 | input | Gate 2 input B. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 6 | Y2 | output | Gate 2 output, Y2 = A2 + B2. Push-pull CMOS output; drives ≤ 4.0 mA at VCC = 4.5 V with VOH ≥ 3.7 V and VOL ≤ 0.4 V. |+| 7 | GND | power_in | Ground reference (0 V). Must be tied to system ground. Absolute-maximum VCC-to-GND current is ±50 mA. |+| 8 | Y3 | output | Gate 3 output, Y3 = A3 + B3. Push-pull CMOS output; drives ≤ 4.0 mA at VCC = 4.5 V with VOH ≥ 3.7 V and VOL ≤ 0.4 V. |+| 9 | A3 | input | Gate 3 input A. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 10 | B3 | input | Gate 3 input B. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 11 | Y4 | output | Gate 4 output, Y4 = A4 + B4. Push-pull CMOS output; drives ≤ 4.0 mA at VCC = 4.5 V with VOH ≥ 3.7 V and VOL ≤ 0.4 V. |+| 12 | A4 | input | Gate 4 input A. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 13 | B4 | input | Gate 4 input B. CMOS logic input; VIH ≥ 3.15 V and VIL ≤ 1.35 V at VCC = 4.5 V. Input leakage ≤ 1 µA. |+| 14 | VCC | power_in | Positive supply. Operating range 2.0 V to 6.0 V (typ 5 V); absolute-maximum 6.5 V. Bypass with a 0.1 µF ceramic close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | GR |+| Package | SOP-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `74HC32SS`+- `74HC32SD`++## CAD (KiCad official)++- Symbol: `74HC32S`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOP-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [GR datasheet](docs/74hc32s-datasheet.pdf) (None pp, sha256 `3c3c9b0cfcda2c81`, retrieved 2026-08-17, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc32s-datasheet.pdf)

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