component
74HC273PW
Public Made by Adomby adom
Nexperia Flip Flops, TSSOP-20. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+202−8@@ -1,13 +1,212 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74hc273pw",+ "title": "74HC273PW",+ "brief": "Nexperia Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Flip Flops, TSSOP-20. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74hc273pw" ],+ "component": {+ "mpn": "74HC273PW",+ "manufacturer": "Nexperia",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Logic",+ "subcategory": "Flip Flops",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC273PW.pdf",+ "parts": {+ "symbol": "74hc273pw.kicad_sym",+ "footprint": "74hc273pw.kicad_mod",+ "model_3d": "74hc273pw.glb",+ "model_3d_step": "74hc273pw.step",+ "lbr": "74hc273pw.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "MR",+ "type": "input",+ "description": "Master reset input, active LOW. A LOW on MR asynchronously forces all eight Qn outputs LOW, overriding the clock and Dn inputs."+ },+ {+ "number": "2",+ "name": "Q0",+ "type": "output",+ "description": "Flip-flop 0 output. Latches the state of D0 on the LOW-to-HIGH transition of CP; forced LOW when MR is LOW."+ },+ {+ "number": "3",+ "name": "D0",+ "type": "input",+ "description": "Data input to flip-flop 0. Sampled on the rising edge of CP subject to setup and hold times."+ },+ {+ "number": "4",+ "name": "D1",+ "type": "input",+ "description": "Data input to flip-flop 1. Sampled on the rising edge of CP."+ },+ {+ "number": "5",+ "name": "Q1",+ "type": "output",+ "description": "Flip-flop 1 output. Latches D1 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "6",+ "name": "Q2",+ "type": "output",+ "description": "Flip-flop 2 output. Latches D2 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "7",+ "name": "D2",+ "type": "input",+ "description": "Data input to flip-flop 2. Sampled on the rising edge of CP."+ },+ {+ "number": "8",+ "name": "D3",+ "type": "input",+ "description": "Data input to flip-flop 3. Sampled on the rising edge of CP."+ },+ {+ "number": "9",+ "name": "Q3",+ "type": "output",+ "description": "Flip-flop 3 output. Latches D3 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "10",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference, 0 V."+ },+ {+ "number": "11",+ "name": "CP",+ "type": "input",+ "description": "Clock input, positive-edge triggered. All eight flip-flops latch their Dn inputs on the LOW-to-HIGH transition of CP."+ },+ {+ "number": "12",+ "name": "Q4",+ "type": "output",+ "description": "Flip-flop 4 output. Latches D4 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "13",+ "name": "D4",+ "type": "input",+ "description": "Data input to flip-flop 4. Sampled on the rising edge of CP."+ },+ {+ "number": "14",+ "name": "D5",+ "type": "input",+ "description": "Data input to flip-flop 5. Sampled on the rising edge of CP."+ },+ {+ "number": "15",+ "name": "Q5",+ "type": "output",+ "description": "Flip-flop 5 output. Latches D5 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "16",+ "name": "Q6",+ "type": "output",+ "description": "Flip-flop 6 output. Latches D6 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "17",+ "name": "D6",+ "type": "input",+ "description": "Data input to flip-flop 6. Sampled on the rising edge of CP."+ },+ {+ "number": "18",+ "name": "D7",+ "type": "input",+ "description": "Data input to flip-flop 7. Sampled on the rising edge of CP."+ },+ {+ "number": "19",+ "name": "Q7",+ "type": "output",+ "description": "Flip-flop 7 output. Latches D7 on the rising edge of CP; forced LOW when MR is LOW."+ },+ {+ "number": "20",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage. 2.0 V to 6.0 V for 74HC273 (4.5 V to 5.5 V for 74HCT273)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74HC273PW.pdf",+ "pages": 17,+ "sha256": "dac5acf608742f73",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "TSSOP-20",+ "Category": "Logic",+ "Pins": "20"+ }+ },+ "variants": [+ {+ "mpn": "74HC273PW",+ "kind": "packaging"+ },+ {+ "mpn": "74HC273PWD",+ "kind": "packaging"+ },+ {+ "mpn": "74HC273PWBQ",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74hc273pw"+ ],+ "discovery_pitch": "74HC273PW (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +224,5 @@ "docs/74hc273pw-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }