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Initial commit: component/74hc21d

Ray ·85a6442367 ·1mo ago
2 files changed +90
README.mdadded+56
@@ -0,0 +1,56 @@+# 74HC21D++**Nexperia** · Gates · SOIC-14++74HC21D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Data input A of AND gate 1. CMOS input level referenced to V_CC; includes input clamp diode. |+| 2 | 1B | input | Data input B of AND gate 1. CMOS input level referenced to V_CC; includes input clamp diode. |+| 3 | N.C. | unconnected | Not connected. Leave floating or tie to a defined potential; no internal bond. |+| 4 | 1C | input | Data input C of AND gate 1. CMOS input level referenced to V_CC; includes input clamp diode. |+| 5 | 1D | input | Data input D of AND gate 1. CMOS input level referenced to V_CC; includes input clamp diode. |+| 6 | 1Y | output | Data output of AND gate 1 (1Y = 1A · 1B · 1C · 1D). Push-pull CMOS output, ±25 mA absolute maximum. |+| 7 | GND | power_in | Ground reference (0 V). |+| 8 | 2Y | output | Data output of AND gate 2 (2Y = 2A · 2B · 2C · 2D). Push-pull CMOS output, ±25 mA absolute maximum. |+| 9 | 2A | input | Data input A of AND gate 2. CMOS input level referenced to V_CC; includes input clamp diode. |+| 10 | 2B | input | Data input B of AND gate 2. CMOS input level referenced to V_CC; includes input clamp diode. |+| 11 | N.C. | unconnected | Not connected. Leave floating or tie to a defined potential; no internal bond. |+| 12 | 2C | input | Data input C of AND gate 2. CMOS input level referenced to V_CC; includes input clamp diode. |+| 13 | 2D | input | Data input D of AND gate 2. CMOS input level referenced to V_CC; includes input clamp diode. |+| 14 | VCC | power_in | Supply voltage, 2.0 V to 6.0 V (5.0 V typ). Absolute max 7 V. Bypass locally to GND with a 100 nF ceramic capacitor. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++Same part, different packaging or reel option.++- `74HC21DD`+- `74HC21DPW`++## CAD (KiCad official)++- Symbol: `74HC21D`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC21D.pdf) (11 pp, sha256 `1f36967884668dca`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc21d-datasheet.pdf)
page.jsonadded+34
@@ -0,0 +1,34 @@+{+  "slug": "74hc21d",+  "version": "0.1.0",+  "type": "component",+  "description": "Nexperia Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "logic",+    "74hc21d"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "74hc21d.kicad_sym",+    "74hc21d.kicad_mod",+    "74hc21d.glb",+    "74hc21d.step",+    "74hc21d.lbr",+    "docs/hero.png",+    "docs/74hc21d-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html"+  ],+  "visibility": "public",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file