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74hc164pw: factory component page (tier=mfr)

Ray ·c78b5a0683 ·2mo ago ·parent cd18d6d
1 file changed +152−8
page.json+152−8
@@ -1,13 +1,162 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "74hc164pw",+  "title": "74HC164PW",+  "brief": "Nexperia Shifting Register, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Nexperia Shifting Register, TSSOP-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "74hc164pw"   ],+  "component": {+    "mpn": "74HC164PW",+    "manufacturer": "Nexperia",+    "package": "TSSOP-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Shifting Register",+    "datasheet": "https://assets.nexperia.com/documents/data-sheet/74HC164PW.pdf",+    "parts": {+      "symbol": "74hc164pw.kicad_sym",+      "footprint": "74hc164pw.kicad_mod",+      "model_3d": "74hc164pw.glb",+      "model_3d_step": "74hc164pw.step",+      "lbr": "74hc164pw.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "DSA",+        "type": "input",+        "description": "Gated serial data input A. AND-combined with DSB to feed the first flip-flop; either input can serve as an active-HIGH enable for the other. Data must meet set-up/hold before the LOW-to-HIGH CP transition."+      },+      {+        "number": "2",+        "name": "DSB",+        "type": "input",+        "description": "Gated serial data input B. AND-combined with DSA to feed the first flip-flop; either input can serve as an active-HIGH enable for the other."+      },+      {+        "number": "3",+        "name": "Q0",+        "type": "output",+        "description": "Parallel data output, bit 0 (first stage of the shift register). CMOS push-pull output."+      },+      {+        "number": "4",+        "name": "Q1",+        "type": "output",+        "description": "Parallel data output, bit 1. CMOS push-pull output."+      },+      {+        "number": "5",+        "name": "Q2",+        "type": "output",+        "description": "Parallel data output, bit 2. CMOS push-pull output."+      },+      {+        "number": "6",+        "name": "Q3",+        "type": "output",+        "description": "Parallel data output, bit 3. CMOS push-pull output."+      },+      {+        "number": "7",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference (0 V)."+      },+      {+        "number": "8",+        "name": "CP",+        "type": "input",+        "description": "Clock input. Data is shifted on the LOW-to-HIGH edge (edge-triggered). Maximum frequency typically 78 MHz at Vcc=5 V."+      },+      {+        "number": "9",+        "name": "MR",+        "type": "input",+        "description": "Master reset input, active LOW. Asynchronously clears the register and forces all Q outputs LOW, independent of CP."+      },+      {+        "number": "10",+        "name": "Q4",+        "type": "output",+        "description": "Parallel data output, bit 4. CMOS push-pull output."+      },+      {+        "number": "11",+        "name": "Q5",+        "type": "output",+        "description": "Parallel data output, bit 5. CMOS push-pull output."+      },+      {+        "number": "12",+        "name": "Q6",+        "type": "output",+        "description": "Parallel data output, bit 6. CMOS push-pull output."+      },+      {+        "number": "13",+        "name": "Q7",+        "type": "output",+        "description": "Parallel data output, bit 7 (last stage of the shift register). CMOS push-pull output."+      },+      {+        "number": "14",+        "name": "VCC",+        "type": "power_in",+        "description": "Positive supply voltage. 74HC164: 2.0 to 6.0 V (recommended). 74HCT164: 4.5 to 5.5 V."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://assets.nexperia.com/documents/data-sheet/74HC164PW.pdf",+        "pages": 16,+        "sha256": "aa299aaeb852d99f",+        "source_tier": "mfr"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Nexperia",+      "Package": "TSSOP-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "74hc164pw"+  ],+  "discovery_pitch": "74HC164PW (Nexperia) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +174,5 @@     "docs/74hc164pw-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file