component
74HC08DMT
Public Made by Adomby adom
HGSEMI Gates, TSSOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
pin 1: carry the footprint's marker into the .lbr, the viewer and page.json (silk-marker, drawn, top-left)
2 files changed
+447−1
package.json+2−1@@ -24,6 +24,7 @@ "docs/hero.png", "docs/74hc08dmt-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ] }
pads.jsonadded+445@@ -0,0 +1,445 @@+{+ "schema": "adom.pads/1",+ "slug": "74hc08dmt",+ "footprint": "TSSOP-14_4.4x5mm_P0.65mm",+ "generated_from": {+ "footprint": "TSSOP-14_4.4x5mm_P0.65mm@sha256:e4bf82cea6d3b325",+ "pins": "page.json:component.pins",+ "overrides": null+ },+ "pin1": {+ "pad": "1",+ "at": [+ -2.8625,+ -1.95+ ],+ "corner": "top-left",+ "source": "silk-marker",+ "derived_from": "TSSOP-14_4.4x5mm_P0.65mm@sha256:e4bf82cea6d3b325"+ },+ "pad_count": 14,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+ {+ "pad": "1",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -1.95+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "1",+ "name": "A1",+ "type": "input",+ "description": "Input A of gate 1 (AND gate 1). CMOS logic input; VIH >= 4.2V @ VCC=6V.",+ "is_pin1": true,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "2",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -1.3+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "2",+ "name": "B1",+ "type": "input",+ "description": "Input B of gate 1 (AND gate 1). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "3",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ -0.65+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "3",+ "name": "Y1",+ "type": "output",+ "description": "Output Y of gate 1. Push-pull output, Y1 = A1 AND B1. Drive capability |IOUT| <= 5.2 mA @ VCC=6V.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "4",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "4",+ "name": "A2",+ "type": "input",+ "description": "Input A of gate 2 (AND gate 2). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "5",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 0.65+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "5",+ "name": "B2",+ "type": "input",+ "description": "Input B of gate 2 (AND gate 2). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "6",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 1.3+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "6",+ "name": "Y2",+ "type": "output",+ "description": "Output Y of gate 2. Push-pull output, Y2 = A2 AND B2.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "7",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ -2.8625,+ 1.95+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Return for VCC supply current (ICC max 50 mA).",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "8",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 1.95+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "8",+ "name": "Y3",+ "type": "output",+ "description": "Output Y of gate 3. Push-pull output, Y3 = A3 AND B3.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "9",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 1.3+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "9",+ "name": "A3",+ "type": "input",+ "description": "Input A of gate 3 (AND gate 3). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "10",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 0.65+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "10",+ "name": "B3",+ "type": "input",+ "description": "Input B of gate 3 (AND gate 3). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "11",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ 0.0+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "11",+ "name": "Y4",+ "type": "output",+ "description": "Output Y of gate 4. Push-pull output, Y4 = A4 AND B4.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "12",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -0.65+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "12",+ "name": "A4",+ "type": "input",+ "description": "Input A of gate 4 (AND gate 4). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "13",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -1.3+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "13",+ "name": "B4",+ "type": "input",+ "description": "Input B of gate 4 (AND gate 4). CMOS logic input.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ },+ {+ "pad": "14",+ "kind": "smd",+ "shape": "roundrect",+ "at": [+ 2.8625,+ -1.95+ ],+ "rot": 0.0,+ "size": [+ 1.475,+ 0.4+ ],+ "layers": [+ "F.Cu",+ "F.Mask",+ "F.Paste"+ ],+ "thermal": false,+ "pin": "14",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 2.0 V to 6.0 V (absolute max 6.5 V). Quiescent ICC <= 5.5 uA @ VCC=6 V, TA=25 C.",+ "is_pin1": false,+ "source": {+ "geometry": "TSSOP-14_4.4x5mm_P0.65mm.kicad_mod",+ "meaning": "page.json:component.pins",+ "correspondence": "kicad: symbol pin number == pad name"+ }+ }+ ]+}