component
74HC04D
Public Made by Adomby adom
Nexperia Inverters, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+56@@ -0,0 +1,56 @@+# 74HC04D++**Nexperia** · Inverters · SOIC-14++74HC04D from Nexperia, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Data input to inverter 1. CMOS logic level input; VIH min = 3.15 V and VIL max = 1.35 V at VCC = 4.5 V. Input leakage current ±0.1 μA typ. |+| 2 | 1Y | output | Data output from inverter 1 (logical inversion of 1A). Push-pull CMOS output rated for IO = ±5.2 mA at VCC = 6.0 V with VOH ≥ 5.48 V and VOL ≤ 0.26 V. |+| 3 | 2A | input | Data input to inverter 2. CMOS logic level input with clamp diodes to VCC and GND. |+| 4 | 2Y | output | Data output from inverter 2 (logical inversion of 2A). Push-pull CMOS output. |+| 5 | 3A | input | Data input to inverter 3. CMOS logic level input with clamp diodes to VCC and GND. |+| 6 | 3Y | output | Data output from inverter 3 (logical inversion of 3A). Push-pull CMOS output. |+| 7 | GND | power_in | Ground reference (0 V). All voltages in the datasheet are referenced to this pin. |+| 8 | 4Y | output | Data output from inverter 4 (logical inversion of 4A). Push-pull CMOS output. |+| 9 | 4A | input | Data input to inverter 4. CMOS logic level input with clamp diodes to VCC and GND. |+| 10 | 5Y | output | Data output from inverter 5 (logical inversion of 5A). Push-pull CMOS output. |+| 11 | 5A | input | Data input to inverter 5. CMOS logic level input with clamp diodes to VCC and GND. |+| 12 | 6Y | output | Data output from inverter 6 (logical inversion of 6A). Push-pull CMOS output. |+| 13 | 6A | input | Data input to inverter 6. CMOS logic level input with clamp diodes to VCC and GND. |+| 14 | VCC | power_in | Positive supply voltage. Recommended operating range 2.0 V to 6.0 V for 74HC04 (4.5 V to 5.5 V for 74HCT04). Bypass with a 100 nF ceramic capacitor to GND close to the pin. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Nexperia |+| Package | SOIC-14 |+| Category | Logic |+| Pins | 14 |++## Ordering variants++- `74HC04DD`+- `74HC04DPW`+- `74HC04DBQ`+- `74HC04DBZ`++## CAD (KiCad official)++- Symbol: `74HC04D`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Nexperia datasheet](https://assets.nexperia.com/documents/data-sheet/74HC04D.pdf) (15 pp, sha256 `378aac1a6ecb8e2c`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74hc04d-datasheet.pdf)
page.jsonadded+34@@ -0,0 +1,34 @@+{+ "slug": "74hc04d",+ "version": "0.1.0",+ "type": "component",+ "description": "Nexperia Inverters, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "74hc04d"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "74hc04d.kicad_sym",+ "74hc04d.kicad_mod",+ "74hc04d.glb",+ "74hc04d.step",+ "74hc04d.lbr",+ "docs/hero.png",+ "docs/74hc04d-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "visibility": "public",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}