component
74AHCT594PW
Public Made by Adomby adom
Nexperia Shift Registers, TSSOP-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
page.json+178−8@@ -1,13 +1,188 @@ {+ "schema_version": 1,+ "type": "component", "slug": "74ahct594pw",+ "title": "74AHCT594PW",+ "brief": "Nexperia Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "Nexperia Shift Registers, TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "logic", "74ahct594pw" ],+ "component": {+ "mpn": "74AHCT594PW",+ "manufacturer": "Nexperia",+ "package": "TSSOP-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://assets.nexperia.com/documents/data-sheet/74AHCT594PW.pdf",+ "parts": {+ "symbol": "74ahct594pw.kicad_sym",+ "footprint": "74ahct594pw.kicad_mod",+ "model_3d": "74ahct594pw.glb",+ "model_3d_step": "74ahct594pw.step",+ "lbr": "74ahct594pw.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Q1",+ "type": "output",+ "description": "Parallel data output bit 1 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V (VOL \u2264 0.44 V)."+ },+ {+ "number": "2",+ "name": "Q2",+ "type": "output",+ "description": "Parallel data output bit 2 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "3",+ "name": "Q3",+ "type": "output",+ "description": "Parallel data output bit 3 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "4",+ "name": "Q4",+ "type": "output",+ "description": "Parallel data output bit 4 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "5",+ "name": "Q5",+ "type": "output",+ "description": "Parallel data output bit 5 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "6",+ "name": "Q6",+ "type": "output",+ "description": "Parallel data output bit 6 from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "7",+ "name": "Q7",+ "type": "output",+ "description": "Parallel data output bit 7 (MSB) from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference (0 V). Maximum ground current 75 mA."+ },+ {+ "number": "9",+ "name": "Q7S",+ "type": "output",+ "description": "Serial data output - the last stage of the shift register (before the storage latch). Used for cascading additional 74AHCT594 devices; changes on rising edge of SHCP."+ },+ {+ "number": "10",+ "name": "SHR",+ "type": "input",+ "description": "Shift-register reset input, active LOW (asynchronous). Driving SHR LOW clears the internal 8-bit shift register only; the storage register is unaffected. Schmitt-trigger TTL-compatible input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "11",+ "name": "SHCP",+ "type": "input",+ "description": "Shift-register clock input. Data on DS is shifted into the shift register on the LOW-to-HIGH transition. Schmitt-trigger TTL-compatible input; fmax \u2265 70 MHz at VCC = 4.5 V-5.5 V."+ },+ {+ "number": "12",+ "name": "STCP",+ "type": "input",+ "description": "Storage-register clock input. On the LOW-to-HIGH transition, the contents of the shift register are latched into the 8-bit storage register and appear on Q0-Q7. Schmitt-trigger TTL-compatible input."+ },+ {+ "number": "13",+ "name": "STR",+ "type": "input",+ "description": "Storage-register reset input, active LOW (asynchronous). Driving STR LOW forces all parallel outputs Q0-Q7 LOW; the shift register is unaffected. Schmitt-trigger TTL-compatible input, overvoltage tolerant to 5.5 V."+ },+ {+ "number": "14",+ "name": "DS",+ "type": "input",+ "description": "Serial data input to the shift register. Sampled on the LOW-to-HIGH transition of SHCP. tsu = 3 ns, th = 2 ns (VCC = 4.5 V). Schmitt-trigger TTL-compatible input."+ },+ {+ "number": "15",+ "name": "Q0",+ "type": "output",+ "description": "Parallel data output bit 0 (LSB) from the 8-bit storage register. CMOS push-pull output; drive capability up to 8 mA at VCC = 4.5 V."+ },+ {+ "number": "16",+ "name": "VCC",+ "type": "power_in",+ "description": "Positive supply voltage. Operating range 4.5 V to 5.5 V for the 74AHCT594 (TTL-level inputs). Absolute maximum 7.0 V."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://assets.nexperia.com/documents/data-sheet/74AHCT594PW.pdf",+ "pages": 19,+ "sha256": "904f218d5c3a23ea",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "Nexperia",+ "Package": "TSSOP-16",+ "Category": "Logic",+ "Pins": "16"+ }+ },+ "variants": [+ {+ "mpn": "74AHCT594PW",+ "kind": "packaging"+ },+ {+ "mpn": "74AHCT594PWD",+ "kind": "packaging"+ },+ {+ "mpn": "74AHCT594PWBQ",+ "kind": "packaging"+ }+ ],+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "74ahct594pw"+ ],+ "discovery_pitch": "74AHCT594PW (Nexperia) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +200,5 @@ "docs/74ahct594pw-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }