component
74ACT11000DR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# 74ACT11000DR++**Texas Instruments** · Logic Gates · SOIC-16++74ACT11000DR from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | 1A | input | Input A of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 2 | 1Y | output | Output of NAND gate 1, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL). |+| 3 | 2Y | output | Output of NAND gate 2, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL). |+| 4 | GND | power_in | Ground reference for the device; one of two GND pins that should both be connected. |+| 5 | GND | power_in | Ground reference for the device; one of two GND pins that should both be connected. |+| 6 | 3Y | output | Output of NAND gate 3, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL). |+| 7 | 4Y | output | Output of NAND gate 4, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL). |+| 8 | 4B | input | Input B of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 9 | 4A | input | Input A of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 10 | 3B | input | Input B of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 11 | 3A | input | Input A of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 12 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected. |+| 13 | VCC | power_in | Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected. |+| 14 | 2B | input | Input B of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 15 | 2A | input | Input A of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |+| 16 | 1B | input | Input B of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `74ACT11000DR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `74act11000dr-etched.step` / `74act11000dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `74act11000dr.step` / `74act11000dr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/74act11000.pdf) (10 pp, sha256 `12ce66baa18c48d4`, retrieved 2026-10-08, tier: manufacturer)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/74act11000dr-datasheet.pdf)
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TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "2",+ "name": "1Y",+ "type": "output",+ "description": "Output of NAND gate 1, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."+ },+ {+ "number": "3",+ "name": "2Y",+ "type": "output",+ "description": "Output of NAND gate 2, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device; one of two GND pins that should both be connected."+ },+ {+ "number": "5",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference for the device; one of two GND pins that should both be connected."+ },+ {+ "number": "6",+ "name": "3Y",+ "type": "output",+ "description": "Output of NAND gate 3, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."+ },+ {+ "number": "7",+ "name": "4Y",+ "type": "output",+ "description": "Output of NAND gate 4, Y = A·B in positive logic; sources up to -24 mA (IOH) and sinks up to 24 mA (IOL)."+ },+ {+ "number": "8",+ "name": "4B",+ "type": "input",+ "description": "Input B of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "9",+ "name": "4A",+ "type": "input",+ "description": "Input A of NAND gate 4; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "10",+ "name": "3B",+ "type": "input",+ "description": "Input B of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "11",+ "name": "3A",+ "type": "input",+ "description": "Input A of NAND gate 3; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "12",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected."+ },+ {+ "number": "13",+ "name": "VCC",+ "type": "power_in",+ "description": "Supply voltage, 4.5 V to 5.5 V recommended; one of two VCC pins that should both be connected."+ },+ {+ "number": "14",+ "name": "2B",+ "type": "input",+ "description": "Input B of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "15",+ "name": "2A",+ "type": "input",+ "description": "Input A of NAND gate 2; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ },+ {+ "number": "16",+ "name": "1B",+ "type": "input",+ "description": "Input B of NAND gate 1; TTL-compatible, with VIH minimum 2 V, VIL maximum 0.8 V, and input range 0 V to VCC."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The pin-to-name mapping was reconstructed from scrambled text extraction of the top-view diagram on ; The datasheet pin figure covers the D, J and N packages, and the pin numbers shown are for the D, J ; Pin descriptions are limited to what the datasheet states (logic function, recommended VCC of 4.5 to"+ ],+ "pages_sent": 10,+ "cost_usd": 0.0627,+ "at": "2026-10-08T17:57:34"+ },+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/74act11000.pdf",+ "pages": 10,+ "sha256": "12ce66baa18c48d4",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "74act11000dr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "74act11000dr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f19e0bb34c3d12ee52906036f07886d6c4441af9e329523e89e60ef1893e09f4",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}