π120E30

@@ -0,0 +1,265 @@+{+ "schema": "adom.pads/1",+ "slug": "120e30",+ "footprint": "SOIC-8_3.9x4.9mm_P1.27mm",+ "generated_from": {+  "footprint": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",+  "pins": "page.json:component.pins",+  "overrides": null+ },+ "pin1": {+  "pad": "1",+  "at": [+   -2.475,+   -1.905+  ],+  "corner": "top-left",+  "source": "silk-marker",+  "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4"+ },+ "pad_count": 8,+ "paste_apertures": 0,+ "issues": [],+ "pads": [+  {+   "pad": "1",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    -1.905+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "1",+   "name": "VDD1",+   "type": "power_in",+   "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 µF-10 µF low-ESR ceramic close to the pin.",+   "is_pin1": true,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "2",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    -0.635+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "2",+   "name": "VIA",+   "type": "input",+   "description": "Logic input for channel A (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Absolute max −0.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "3",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    0.635+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "3",+   "name": "VIB",+   "type": "input",+   "description": "Logic input for channel B (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Drives isolated logic output VOB on Side 2. Both π120 channels are forward (Side 1 → Side 2).",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "4",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    -2.475,+    1.905+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "4",+   "name": "GND1",+   "type": "power_in",+   "description": "Ground reference for isolator Side 1. Return for VDD1 bypass and for VIA/VIB input signals. Isolated from GND2 across the on-die iDivider capacitive barrier.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "5",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    1.905+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "5",+   "name": "GND2",+   "type": "power_in",+   "description": "Ground reference for isolator Side 2. Return for VDD2 bypass and for VOA/VOB output signals. Isolated from GND1 (3.0 kVrms withstand for the E3x variant).",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "6",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    0.635+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "6",+   "name": "VOB",+   "type": "output",+   "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix).",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "7",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    -0.635+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "7",+   "name": "VOA",+   "type": "output",+   "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix).",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  },+  {+   "pad": "8",+   "kind": "smd",+   "shape": "roundrect",+   "at": [+    2.475,+    -1.905+   ],+   "rot": 0.0,+   "size": [+    1.95,+    0.6+   ],+   "layers": [+    "F.Cu",+    "F.Mask",+    "F.Paste"+   ],+   "thermal": false,+   "pin": "8",+   "name": "VDD2",+   "type": "power_in",+   "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V ↔ 5 V level translation. Bypass to GND2 with 0.1 µF-10 µF low-ESR ceramic close to the pin.",+   "is_pin1": false,+   "source": {+    "geometry": "SOIC-8_3.9x4.9mm_P1.27mm.kicad_mod",+    "meaning": "page.json:component.pins",+    "correspondence": "kicad: symbol pin number == pad name"+   }+  }+ ]+}\ No newline at end of file