component
π120E30
Public Made by Adomby adom
2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.md+14@@ -43,6 +43,20 @@ - Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm` - 3D model: SOIC-8-N (KiCad packages3D, STEP) +## 3D model downloads++Two STEP files. Same geometry, different body top:++| File | Size | Use it when |+|---|---|---|+| [`120e30.step`](120e30.step) | 122 KB | You want the bare part, or you mark your own boards. |+| [`120e30-etched.step`](120e30-etched.step) | 1.6 MB | You want the part with `120E30` already on it. |++The marking in the etched file is real recessed geometry cut into the solid, not a+texture or a decal: 399 faces against 147 in the bare model. It+survives export, section views, and rendering in any CAD tool, and it drops straight+into KiCad or Fusion with no extra setup.+ ## Provenance Data extracted from the manufacturer datasheet, not a distributor listing:
package.json+1−1@@ -1,6 +1,6 @@ { "slug": "120e30",- "version": "0.1.0",+ "version": "0.2.0", "type": "component", "description": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "tags": [
page.json+16−16@@ -2,17 +2,17 @@ "schema_version": 1, "type": "component", "slug": "120e30",- "title": "\u03c0120E30",+ "title": "π120E30", "brief": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D.",- "version": "0.1.0",+ "version": "0.2.0", "license": "CC-BY-SA-4.0", "tags": [ "component", "pmic",- "\u03c0120e30"+ "π120e30" ], "component": {- "mpn": "\u03c0120E30",+ "mpn": "π120E30", "manufacturer": "2Pai Semi", "package": "SOIC-8-N", "pin_count": 8,@@ -34,19 +34,19 @@ "number": "1", "name": "VDD1", "type": "power_in",- "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 \u00b5F-10 \u00b5F low-ESR ceramic close to the pin."+ "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 µF-10 µF low-ESR ceramic close to the pin." }, { "number": "2", "name": "VIA", "type": "input",- "description": "Logic input for channel A (Side 1). CMOS input, VIH \u2265 0.7\u00b7VDD1, VIL \u2264 0.3\u00b7VDD1. Absolute max \u22120.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2."+ "description": "Logic input for channel A (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Absolute max −0.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2." }, { "number": "3", "name": "VIB", "type": "input",- "description": "Logic input for channel B (Side 1). CMOS input, VIH \u2265 0.7\u00b7VDD1, VIL \u2264 0.3\u00b7VDD1. Drives isolated logic output VOB on Side 2. Both \u03c0120 channels are forward (Side 1 \u2192 Side 2)."+ "description": "Logic input for channel B (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Drives isolated logic output VOB on Side 2. Both π120 channels are forward (Side 1 → Side 2)." }, { "number": "4",@@ -64,19 +64,19 @@ "number": "6", "name": "VOB", "type": "output",- "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated \u00b110 mA absolute max, recommended \u00b16 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."+ "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)." }, { "number": "7", "name": "VOA", "type": "output",- "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated \u00b110 mA absolute max, recommended \u00b16 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."+ "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)." }, { "number": "8", "name": "VDD2", "type": "power_in",- "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V \u2194 5 V level translation. Bypass to GND2 with 0.1 \u00b5F-10 \u00b5F low-ESR ceramic close to the pin."+ "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V ↔ 5 V level translation. Bypass to GND2 with 0.1 µF-10 µF low-ESR ceramic close to the pin." } ], "provenance": {@@ -127,9 +127,9 @@ "info" ], "discovery_triggers": [- "\u03c0120e30"+ "π120e30" ],- "discovery_pitch": "\u03c0120E30 (2Pai Semi) component page with datasheet-verified CAD.",+ "discovery_pitch": "π120E30 (2Pai Semi) component page with datasheet-verified CAD.", "author": { "name": "Ray", "email": "[email protected]"@@ -150,9 +150,9 @@ "docs/hero.png", "docs/120e30-datasheet.pdf", "viewers/symbol.html",- "viewers/footprint.html"+ "viewers/footprint.html",+ "pads.json" ],- "visibility": {- "public": true- }+ "visibility": "public",+ "description": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D." }