π120E30 - Commit - Adom Wiki

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orderable attributes: rebuild .lbr with adom-lbr 2.18.0 so MPN, MANUFACTURER and the distributor part numbers reach <technology> (LCSC_PN C970948). The published library carried no attributes at all, so a BOM had nothing to buy from. Distributor PNs matched on exact MPN AND corroborating manufacturer.

Ray ·5bd84387a7 ·2mo ago ·parent fe57854

2 files changed +34−14

120e30.lbr+20−2 page.json+14−12

120e30.lbr+20−2

@@ -62,6 +62,18 @@   <smd name="6" x="2.4750" y="-0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="7" x="2.4750" y="0.6350" dx="1.9500" dy="0.6000" layer="1"/>   <smd name="8" x="2.4750" y="1.9050" dx="1.9500" dy="0.6000" layer="1"/>+  <polygon width="0.1200" layer="21">+    <vertex x="-2.6000" y="2.4700"/>+    <vertex x="-2.8400" y="2.8000"/>+    <vertex x="-2.3600" y="2.8000"/>+  </polygon>+  <polygon width="0.1000" layer="51">+    <vertex x="-0.9750" y="2.4500"/>+    <vertex x="1.9500" y="2.4500"/>+    <vertex x="1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="-2.4500"/>+    <vertex x="-1.9500" y="1.4750"/>+  </polygon>   <wire x1="-2.0600" y1="2.5600" x2="2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="2.4650" x2="-2.0600" y2="2.5600" width="0.1200" layer="21"/>   <wire x1="-2.0600" y1="-2.5600" x2="-2.0600" y2="-2.4650" width="0.1200" layer="21"/>@@ -70,7 +82,7 @@   <wire x1="2.0600" y1="-2.5600" x2="-2.0600" y2="-2.5600" width="0.1200" layer="21"/>   <text x="0" y="3.480" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>   <text x="0" y="-3.480" size="1.27" layer="27" align="top-center">&gt;VALUE</text>-<!--adom-pin1--><polygon width="0.0500" layer="21"><vertex x="-2.6000" y="2.4700"/><vertex x="-2.8400" y="2.8000"/><vertex x="-2.3600" y="2.8000"/></polygon></package>+</package> </packages> <symbols> <symbol name="π120E30">@@ -108,7 +120,13 @@         <connect gate="G$1" pin="VOB" pad="6"/>         <connect gate="G$1" pin="GND2" pad="5"/>       </connects>-      <technologies><technology name=""/></technologies>+      <technologies>+        <technology name="">+          <attribute name="MPN" value="π120E30" constant="no"/>+          <attribute name="MANUFACTURER" value="2Pai Semi" constant="no"/>+          <attribute name="LCSC_PN" value="C970948" constant="no"/>+        </technology>+      </technologies>     </device>   </devices> </deviceset>

page.json+14−12

@@ -2,17 +2,17 @@   "schema_version": 1,   "type": "component",   "slug": "120e30",-  "title": "π120E30",+  "title": "\u03c0120E30",   "brief": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",   "license": "CC-BY-SA-4.0",   "tags": [     "component",     "pmic",-    "π120e30"+    "\u03c0120e30"   ],   "component": {-    "mpn": "π120E30",+    "mpn": "\u03c0120E30",     "manufacturer": "2Pai Semi",     "package": "SOIC-8-N",     "pin_count": 8,@@ -26,25 +26,27 @@       "model_3d_step": "120e30.step",       "lbr": "120e30.lbr"     },-    "distributor_links": {},+    "distributor_links": {+      "lcsc": "C970948"+    },     "pins": [       {         "number": "1",         "name": "VDD1",         "type": "power_in",-        "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 µF-10 µF low-ESR ceramic close to the pin."+        "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 \u00b5F-10 \u00b5F low-ESR ceramic close to the pin."       },       {         "number": "2",         "name": "VIA",         "type": "input",-        "description": "Logic input for channel A (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Absolute max −0.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2."+        "description": "Logic input for channel A (Side 1). CMOS input, VIH \u2265 0.7\u00b7VDD1, VIL \u2264 0.3\u00b7VDD1. Absolute max \u22120.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2."       },       {         "number": "3",         "name": "VIB",         "type": "input",-        "description": "Logic input for channel B (Side 1). CMOS input, VIH ≥ 0.7·VDD1, VIL ≤ 0.3·VDD1. Drives isolated logic output VOB on Side 2. Both π120 channels are forward (Side 1 → Side 2)."+        "description": "Logic input for channel B (Side 1). CMOS input, VIH \u2265 0.7\u00b7VDD1, VIL \u2264 0.3\u00b7VDD1. Drives isolated logic output VOB on Side 2. Both \u03c0120 channels are forward (Side 1 \u2192 Side 2)."       },       {         "number": "4",@@ -62,19 +64,19 @@         "number": "6",         "name": "VOB",         "type": "output",-        "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."+        "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated \u00b110 mA absolute max, recommended \u00b16 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."       },       {         "number": "7",         "name": "VOA",         "type": "output",-        "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated ±10 mA absolute max, recommended ±6 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."+        "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated \u00b110 mA absolute max, recommended \u00b16 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."       },       {         "number": "8",         "name": "VDD2",         "type": "power_in",-        "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V ↔ 5 V level translation. Bypass to GND2 with 0.1 µF-10 µF low-ESR ceramic close to the pin."+        "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V \u2194 5 V level translation. Bypass to GND2 with 0.1 \u00b5F-10 \u00b5F low-ESR ceramic close to the pin."       }     ],     "provenance": {@@ -125,9 +127,9 @@     "info"   ],   "discovery_triggers": [-    "π120e30"+    "\u03c0120e30"   ],-  "discovery_pitch": "π120E30 (2Pai Semi) component page with datasheet-verified CAD.",+  "discovery_pitch": "\u03c0120E30 (2Pai Semi) component page with datasheet-verified CAD.",   "author": {     "name": "Ray",     "email": "[email protected]"