component
π120E30
Public Made by Adomby adom
2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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page.json+117−9@@ -1,13 +1,126 @@ {+ "schema_version": 1,+ "type": "component", "slug": "120e30",+ "title": "\u03c0120E30",+ "brief": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D.", "version": "0.1.0",- "type": "component",- "description": "2Pai Semi Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-N. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "license": "CC-BY-SA-4.0", "tags": [ "component", "pmic",- "π120e30"+ "\u03c0120e30" ],+ "component": {+ "mpn": "\u03c0120E30",+ "manufacturer": "2Pai Semi",+ "package": "SOIC-8-N",+ "pin_count": 8,+ "category": "PMIC",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2306281036_2Pai-Semi--120E30_C970948.pdf",+ "parts": {+ "symbol": "120e30.kicad_sym",+ "footprint": "120e30.kicad_mod",+ "model_3d": "120e30.glb",+ "model_3d_step": "120e30.step",+ "lbr": "120e30.lbr"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "VDD1",+ "type": "power_in",+ "description": "Supply voltage for isolator Side 1. 3.0 V to 5.5 V operating range; 2.75 V typical undervoltage lockout rising threshold. Bypass to GND1 with 0.1 \u00b5F-10 \u00b5F low-ESR ceramic close to the pin."+ },+ {+ "number": "2",+ "name": "VIA",+ "type": "input",+ "description": "Logic input for channel A (Side 1). CMOS input, VIH \u2265 0.7\u00b7VDD1, VIL \u2264 0.3\u00b7VDD1. Absolute max \u22120.5 V to VDD1 + 0.5 V. Drives isolated logic output VOA on Side 2."+ },+ {+ "number": "3",+ "name": "VIB",+ "type": "input",+ "description": "Logic input for channel B (Side 1). CMOS input, VIH \u2265 0.7\u00b7VDD1, VIL \u2264 0.3\u00b7VDD1. Drives isolated logic output VOB on Side 2. Both \u03c0120 channels are forward (Side 1 \u2192 Side 2)."+ },+ {+ "number": "4",+ "name": "GND1",+ "type": "power_in",+ "description": "Ground reference for isolator Side 1. Return for VDD1 bypass and for VIA/VIB input signals. Isolated from GND2 across the on-die iDivider capacitive barrier."+ },+ {+ "number": "5",+ "name": "GND2",+ "type": "power_in",+ "description": "Ground reference for isolator Side 2. Return for VDD2 bypass and for VOA/VOB output signals. Isolated from GND1 (3.0 kVrms withstand for the E3x variant)."+ },+ {+ "number": "6",+ "name": "VOB",+ "type": "output",+ "description": "Logic output for channel B (Side 2), mirrors VIB across the isolation barrier. Push-pull CMOS output rated \u00b110 mA absolute max, recommended \u00b16 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."+ },+ {+ "number": "7",+ "name": "VOA",+ "type": "output",+ "description": "Logic output for channel A (Side 2), mirrors VIA across the isolation barrier. Push-pull CMOS output rated \u00b110 mA absolute max, recommended \u00b16 mA. Fail-safe LOW when VDD1 unpowered (E30 suffix)."+ },+ {+ "number": "8",+ "name": "VDD2",+ "type": "power_in",+ "description": "Supply voltage for isolator Side 2. 3.0 V to 5.5 V; independent of VDD1 so this pin performs the 3 V \u2194 5 V level translation. Bypass to GND2 with 0.1 \u00b5F-10 \u00b5F low-ESR ceramic close to the pin."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2306281036_2Pai-Semi--120E30_C970948.pdf",+ "pages": 18,+ "sha256": "46f1f75769a4de29",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 8,+ "described": 8,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Manufacturer": "2Pai Semi",+ "Package": "SOIC-8-N",+ "Category": "PMIC",+ "Pins": "8"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "\u03c0120e30"+ ],+ "discovery_pitch": "\u03c0120E30 (2Pai Semi) component page with datasheet-verified CAD.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -25,10 +138,5 @@ "docs/120e30-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }